JAJSS15 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Block Diagram Examples
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Example: Changing Output Frequency
      5. 8.2.5 Crosstalk
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
    2. 9.2 Decoupling Power Supply Inputs
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Device Registers
    1. 12.1 Register Maps
      1. 12.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 12.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 12.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 12.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 12.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 12.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 12.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 12.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 12.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 12.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 12.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 12.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 12.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 12.1.14 R27 Register (Address = 0x1B) [reset = 0x0000]
      15. 12.1.15 R28 Register (Address = 0x1C) [reset = 0x0000]
      16. 12.1.16 R32 Register (Address = 0x20) [reset = 0x0000]
      17. 12.1.17 R33 Register (Address = 0x21) [reset = 0x0000]
      18. 12.1.18 R146 Register (Address = 0x92) [reset = 0x0000]
      19. 12.1.19 R147 Register (Address = 0x93) [reset = 0x0000]
      20. 12.1.20 R148 Register (Address = 0x94) [reset = 0x0000]
      21. 12.1.21 R238 Register (Address = 0xEE) [reset = 0x0000]
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RER|16
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Device Configuration Control

Figure 7-2 shows the relationships between device states, the configuration pins, device initialization, and device operational modes. OTP mode is entered when the REF_CTRL pin is pulled high at start-up. I2C mode is entered when the REF_CTRL pin is pulled low at start-up. In OTP mode, the state of the OTP_SEL0/SCL and OTP_SEL1/SDA pins determines the OTP page that is loaded into the active registers. In I2C mode, the state of the FMT_ADDR pin determines the I2C address of the device, with the OTP_SEL0/SCL and OTP_SEL1/SDA pins re-purposed as I2C clock and data pins, respectively. In I2C mode, the host can update the active device registers, and can program a desired configuration into the EFUSE. The device is one-time programmable, meaning that the register settings can be stored into the internal EFUSE of the device a single time.

The device can be transitioned from OTP to I2C mode, or vice versa, by changing the state of the REF_CTRL pin, then triggering a device power cycle by pulling VDD low, then high again. Alternatively, instead of toggling the VDD pin, the PDN bit (R10[1]) can be set to '1' then '0', or the DEV_IDLE_STATE_SEL bit (R10[4]) can be set to '1' then '0'. Table 7-1 lists the functionality of the configuration pins during OTP and I2C modes.

GUID-20230331-SS0I-LGCV-P285-2C9W515T8BDS-low.svgFigure 7-2 LMK3H0102 Simplified Programming Flow
Table 7-1 Pin Configuration for I2C and OTP Mode
PIN NAMEI2C MODEOTP MODE
FunctionPin StatesFunctionPin States
FMT_ADDROutput Buffer Selection2I2C Address Selection4
OTP_SEL0/SCLOTP Page Selection2I2C Clock Pin2
OTP_SEL1/SDAOTP Page Selection2I2C Data Pin2

In I2C Mode, the device default registers are from the contents of OTP Page 0. In OTP mode, these values come from one of the four OTP pages, selectable based on the state of the OTP_SELx pins on start-up. Figure 7-3 shows interface and control blocks within the LMK3H0102, with the arrows referring to read and write access from the different embedded memories.

GUID-20230430-SS0I-SCBM-L6XM-DXPBBMZVF07W-low.svgFigure 7-3 LMK3H0102 Interface and Control Blocks