If the user wants to change the output
from 100-MHz LP-HCSL on OUT0 and OUT1 to 24-MHz differential LVCMOS clocks on OUT0
and OUT1,- with an additional LVCMOS clock on the REF_CTRL pin, the value of the
BAWFREQ_OFFSET_FIXEDLUT field for this example is 0x3701. The steps for changing the
frequency are as follows:
- Determine the BAW frequency
of the device. This is critical for all following calculations. From Equation 4, if BAWFREQ_OFFSET_FIXEDLUT is 0x3701, then the BAW frequency of this
device is approximately 2471.446441856.
- Determine the channel divider
settings and required FOD frequency. If the output frequency is 24 MHz, and
the range of the FODs is from 100 MHz to 400 MHz, then a channel divider
value of at least 5 is required to generate the output. As there is not a
divide by 5 option, and REF_CLK must also have a clock (see CH0_DIV, CH1_DIV, and REF_CLK_DIV), a divide by 8 is required. From here, 24 MHz times
8 yields an FOD output frequency of 192 MHz. If OUT1 were a different
frequency, then using FOD1 frequency can be required if both frequencies
cannot be generated by dividing down from the same FOD frequency.
- Set the FOD divide values.
Use Equation 1 to calculate the integer divide value FOD0_N_DIV =
floor(2471.446441856/192) = 12. From Equation 2, the numerator divide value FOD0_NUM = int(((2471.446441856/192) - 12) x
224) = 14631693
- Write the desired settings to
the device registers. This includes the divider settings listed above, as
well as the output driver settings. Follow the procedure outlined in Figure 7-4:
- Set PDN = 1.
- Set FOD0_N_DIV = 12
and FOD0_NUM = 14631693.
- Set CH0_DIV, and
REF_CLK_DIV to divide by 8 (by default, OUT1_CH_SEL is set to select
Channel Divider 0).
- Set OUT0_FMT and
OUT1_FMT to select Differential LVCMOS as the output format.
- Set REF_CTRL_PIN_FUNC
to output REF_CLK.
- Set OTP_AUTOLOAD_DIS
to 1 (disable the OTP Page 0 autoload feature).
- Set PDN = 0
The time required for the frequency change to take affect is typically on the order
of 1 ms between issuing PDN = 0 and the output clocks starting at the desired
frequency.