JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
This device supports LP-HCSL (both 85-Ω and 100-Ω internal termination), LVDS, and LVCMOS. For LVCMOS outputs,VDDO can be 1.8 V, 2.5 V or 3.3 V if the VDD is 3.3 V. Otherwise, the VDDO must be the same voltage as VDD.
R6[2:0] / R7[4:2] | Description |
---|---|
0x0 | LP-HCSL 100 Ω Termination (default) |
0x1 | LP-HCSL 85 Ω Termination |
0x2 | AC-coupled LVDS |
0x3 | DC-coupled LVDS |
0x4 |
LVCMOS enabled on OUTx_P LVCMOS disabled on OUTx_N |
0x5 |
LVCMOS disabled on OUTx_P LVCMOS enabled on OUTx_N |
0x6 | LVCMOS enabled on OUTx_P LVCMOS enabled on OUTx_N 180 degrees out of phase (1) |
0x7 | LVCMOS enabled on OUTx_P LVCMOS enabled on OUTx_N OUTx_P and OUTx_N in phase |