JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
R10 is shown in Table 12-23.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PUP_DTC_GAIN_CAL_EN | R/W | 0x0 | Writing a '1' to this bit enables gain calibration on power up. This is recommended for applications where the clock frequencies differ from the default settings. |
14:11 | PROD_REVID | R | 0x0 | Product revision identifier. |
10 | CLK_READY | R | 0x0 | CLK_READY status. The REF_CTRL pin mirrors this status signal when the pin functions as a "clock ready" signal. |
9 | CRC_ERROR | R | 0x0 | This bit indicates if there was a CRC error when programming the EFUSE of the device. If this bit is a '1', then an error has occurred. Outside of EFUSE programming, this bit can be ignored. |
8 | RB_PIN_15 | R | 0x0 | Readback of the REF_CTRL pin. |
7 | RB_PIN_4 | R | 0x0 | Readback of the OTP_SEL1/SDA pin. |
6 | RB_PIN_3 | R | 0x0 | Readback of the OTP_SEL0/SCL pin. |
5 | RB_PIN_2 | R | 0x0 | Readback of the FMT_ADDR pin. |
4 | DEV_IDLE_STATE_SEL | R/W | 0x1 |
This bit controls the behavior of the device when both outputs are disabled. Placing the device into a low-power state is not recommended for PCIe applications, as the time to re-enable the clocks is extended. 0h: When both outputs are disabled, the outputs are muted, and the device is placed into a low-power state. 1h: When both outputs are disabled, the outputs are muted. The device does not enter a low-power state. |
3 | Reserved | R/W | 0x0 | Reserved. Only write '0' to this bit. |
2 | Reserved | R/W | 0x0 | Reserved. Only write '0' to this bit. |
1 | PDN | R/W | 0x0 |
Writing a '1' to this bit forces a power down all analog logic blocks. |
0 | Reserved | R/W | 0x0 | Reserved. Only write '0' to this bit. |