JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
In this mode, I2C is enabled and the SCA and SDL pins function as the I2C clock and I2C data pins, respectively. Table 7-4 shows the four default I2C addresses selectable by the FMT_ADDR pin. The 0xD0, 0xD2, 0xD4, and 0xD8 addresses are with the R/W bit included. The 5 MSBs of the I2C address are set in R12[14:8].
If R12[15] = 1, then the FMT_ADDR pin is ignored, and the I2C address is solely determined by R12[14:8].
REF_CTRL PIN | FMT_ADDR PIN | I2C ADDRESS |
---|---|---|
High | X | N/A (I2C disabled) |
Low | 0 | 0x68 / 0xD0 |
Low | 1 | 0x69 / 0xD2 |
Low | Tied to SDA | 0x6A / 0xD4 |
Low | Tied to SCL | 0x6B / 0xD8 |
When changing the registers of the device, first set PDN = 1 (R10[1] = 1), write to the device registers, then set PDN = 0 (R10[1] = 0).Figure 7-4 shows this process.