JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
R6 is shown in Table 12-23.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | CH1_DIV | R/W | 0x1 | Divider value for Channel Divider 1. 0h: Channel Divider disabled. 1h: FOD / 2 2h: FOD / 4 3h: FOD / 6 4h: FOD / 8 5h: FOD / 10 6h: FOD / 20 7h: FOD / 40 |
12:5 | FOD1_NUM[23:16] | R/W | 0x55 | High byte of the FOD1 fractional divide value. |
4:3 | OUT0_SLEW_RATE | R/W | 0x0 | Slew rate control for OUT0. Only applies to differential output formats. 0h: Between 2.3 and 3.4 V/ns. 1h: Between 2.0 and 3.0 V/ns. 2h: Between 1.7 and 2.7 V/ns. 3h: Between 1.4 and 2.5 V/ns. |
2:0 | OUT0_FMT | R/W | 0x0 | Selects the output format for OUT0. 0h: LP-HCSL 100 Ω Termination. 1h: LP-HCSL 85 Ω Termination. 2h: AC-coupled LVDS. 3h: DC-coupled LVDS. 4h: LVCMOS, OUTx_P enabled, OUTx_N disabled. 5h: LVCMOS, OUTx_P disabled, OUTx_N enabled. 6h: LVCMOS, OUTx_P enabled, OUTx_N enabled, 180 degrees out of phase. 7h: LVCMOS, OUTx_P enabled, OUTx_N enabled, OUTx_P and OUTx_N in phase. |