JAJSS15 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Block Diagram Examples
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Example: Changing Output Frequency
      5. 8.2.5 Crosstalk
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
    2. 9.2 Decoupling Power Supply Inputs
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Device Registers
    1. 12.1 Register Maps
      1. 12.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 12.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 12.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 12.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 12.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 12.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 12.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 12.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 12.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 12.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 12.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 12.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 12.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 12.1.14 R27 Register (Address = 0x1B) [reset = 0x0000]
      15. 12.1.15 R28 Register (Address = 0x1C) [reset = 0x0000]
      16. 12.1.16 R32 Register (Address = 0x20) [reset = 0x0000]
      17. 12.1.17 R33 Register (Address = 0x21) [reset = 0x0000]
      18. 12.1.18 R146 Register (Address = 0x92) [reset = 0x0000]
      19. 12.1.19 R147 Register (Address = 0x93) [reset = 0x0000]
      20. 12.1.20 R148 Register (Address = 0x94) [reset = 0x0000]
      21. 12.1.21 R238 Register (Address = 0xEE) [reset = 0x0000]
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RER|16
サーマルパッド・メカニカル・データ
発注情報

12.1.8 R7 Register (Address = 0x7) [reset = 0x6503]

R7 is shown in Table 12-23.

Return to the Summary Table.

Table 12-10 R7 Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R 0x0 Reserved
14:13 REF_CTRL_PIN_FUNC R/W 0x3

Sets the function of the REF_CTRL pin.

0h: REF_CTRL pin disabled, pulled to GND.

1h: REF_CTRL pin disabled, tri-state.

2h: REF_CTRL pin functions as an additional LVCMOS REF_CLK output.

3h: REF_CTRL pin functions as "clock ready" signal.
12:11 REF_CLK_DIV R/W 0x0

REF_CLK output divisor value when REF_CTRL is used as REF_CLK.

0h: REF_CLK disabled.

1h: FOD / 2.

2h: FOD / 4.

3h: FOD / 8.
10 Reserved R/W 0x1 Reserved. Do not write any value other than '1' to this field.
9 REF_CLK_FOD_SEL R/W 0x0

Select the FOD used to generate the REF_CLK output.

0h: FOD0.

1h: FOD1.
8 OUT1_EN R/W 0x1

Output Enable bit for OUT1.

0h: OUT1 is disabled.

1h: OUT1 is enabled.
7 OUT1_CH_SEL R/W 0x0

Selects the source for OUT1. If the Edge Combiner is enabled, then this bit is ignored.

0h: OUT1 is sourced from Channel Divider 0.

1h: OUT1 is sourced from Channel Divider 1.
6:5 OUT1_SLEW_RATE R/W 0x0

Slew rate control for OUT01

Only applies to differential output formats.

0h: Between 2.3 and 3.4 V/ns.

1h: Between 2.0 and 3.0 V/ns.

2h: Between 1.7 and 2.7 V/ns.

3h: Between 1.4 and 2.5 V/ns.
4:2 OUT1_FMT R/W 0x0

Selects the output format for OUT1.

0h: LP-HCSL 100-Ω Termination.

1h: LP-HCSL 85-Ω Termination.

2h: AC-coupled LVDS.

3h: DC-coupled LVDS.

4h: LVCMOS, OUTx_P enabled, OUTx_N disabled.

5h: LVCMOS, OUTx_P disabled, OUTx_N enabled.

6h: LVCMOS, OUTx_P enabled, OUTx_N enabled, 180 degrees out of phase.

7h: LVCMOS, OUTx_P enabled, OUTx_N enabled, OUTx_P and OUTx_N in phase.
1 OUT0_EN R/W 0x1

Output Enable bit for OUT0.

0h: OUT0 is disabled.

1h: OUT0 is enabled.
0 OE_PIN_POLARITY R/W 0x1

OE pin polarity selection. This bit does not affect the polarity of the OUTx_EN bits, only the OE pin.

0h: OE is active high (OE tied to VDD enables outputs).

1h: OE is active low (OE tied to GND enables outputs).