JAJSS15 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Block Diagram Examples
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Example: Changing Output Frequency
      5. 8.2.5 Crosstalk
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
    2. 9.2 Decoupling Power Supply Inputs
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Device Registers
    1. 12.1 Register Maps
      1. 12.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 12.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 12.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 12.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 12.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 12.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 12.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 12.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 12.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 12.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 12.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 12.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 12.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 12.1.14 R27 Register (Address = 0x1B) [reset = 0x0000]
      15. 12.1.15 R28 Register (Address = 0x1C) [reset = 0x0000]
      16. 12.1.16 R32 Register (Address = 0x20) [reset = 0x0000]
      17. 12.1.17 R33 Register (Address = 0x21) [reset = 0x0000]
      18. 12.1.18 R146 Register (Address = 0x92) [reset = 0x0000]
      19. 12.1.19 R147 Register (Address = 0x93) [reset = 0x0000]
      20. 12.1.20 R148 Register (Address = 0x94) [reset = 0x0000]
      21. 12.1.21 R238 Register (Address = 0xEE) [reset = 0x0000]
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RER|16
サーマルパッド・メカニカル・データ
発注情報

5.6 I2C Interface Specification

All timing requirements referred to VIH-min and VIL-max. Chip VDD = I2C VDD.
PARAMETER TEST CONDITIONS STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
VIL Input low voltage –0.3 0.3 × VDD –0.3 0.3 × VDD V
VIH Input high voltage 0.7 × VDD VDD + 0.3 0.7 × VDD VDD + 0.3 V
Vhys Hysteresis of Schmitt trigger input 0.05 × VDD V
VOL1 Low level output voltage 1 At 3 mA sink current. VDD > 2 V 0 0.4 0 0.4 V
VOL2 Low level output voltage 2 At 2 mA sink current. VDD ≤ 2 V 0 0.2 x VDD V
IOL Low level output current VOL = 0.4 V 3 3 mA
VOL = 0.6 V 6 mA
tOF Output fall time from VIHmin to VILmax 250 20 × (VDD / 5.5 V) 250 ns
tSP Pulse width of spikes that must be suppressed by the input filter 0 50 ns
Ii Input current each I/O pin 0.1 × VDD < VIN < 0.9 × VDDmax –10 10 –10 10 µA
Ci Capacitance for each I/O pin 10 10 pF
fSCL SCL clock frequency 0 100 0 400 kHz
tHD-STA Hold time (repeated) START condition After this period, the first clock pulse is generated 4 0.6 µs
tlow Low period of the SCL clock 4.7 1.3 µs
thigh High period of the SCL clock 4 0.6 µs
tSU-STA Set-up time for a repeated START condition 4.7 0.6 µs
tHD-DAT Data hold time I2C bus devices 0 0 µs
tSU-DAT Data set-up time 0.25 0.1 µs
tR Rise time of both SDA and SCL signals 1000 20 300 ns
tF Fall time of both SDA and SCL signals 1000 20 × (VDD / 5.5 V) 300 ns
tSU-STO Set-up time for STOP condition 4 0.6 µs
tBUF Bus free time between a STOP and START condition 4.7 1.3 µs
CB Capacitive load for each bus line 400 400 pF
tVD-DAT Data valid time 3.45 0.9 µs
tVD-ACK Data valid acknowledge time 3.45 0.9 µs
VNL Noise margin at the low level For each connected device, including hysteresis 0.1 x VDD 0.1 × VDD V
VNH Noise margin at the high level For each connected device, including hysteresis 0.2 x VDD 0.2 × VDD V