Enable the edge combiner to generate output frequencies greater than 200 MHz. To use the edge combiner, both FODs must operate at the same exact frequency (that is, the divide values must match). Using the edge combiner bypasses the channel dividers, meaning that the output of both channels comes directly from the edge combiner. When the edge combiner is enabled, FOD0 and FOD1 become 180 degrees out of phase. The edge combiner functions similarly to an SR flip flop, where the rising edge of FOD0 is the "Set" signal, and the rising edge of FOD1 is the "Reset" signal. SSC on FOD0 is not supported when using the edge combiner. Either of the FODs can still generate the LVCMOS REF_CLK output.

For edge combiner operation, the following conditions must be true:

• R0[9:3] and R3[15:9] (integer portion of the FODs) must match.
• R1[15:8] and R6[12:5] (MSB of the fractional numerators) must match.
• R2[15:0] and R8[15:0] (LSBs of the fractional denominators) must match.
• R3[3] or R3[7] (dual FOD enable) must be set to '1'.
• The gain calibration codes for both FODs must be averaged. For example, if DTC1_GAIN_RT = 200, and DTC2_GAIN_RT = 220, then both of these fields must be written to 210. See R146, R147, and R148 for more information.
• If the edge combiner is used for OUT1 only, R3[4] (Channel Divider 0 input selection) must always be set to '0' (FOD0), regardless of the disable state of OUT0.