JAJSS15 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Block Diagram Examples
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Example: Changing Output Frequency
      5. 8.2.5 Crosstalk
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
    2. 9.2 Decoupling Power Supply Inputs
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Device Registers
    1. 12.1 Register Maps
      1. 12.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 12.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 12.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 12.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 12.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 12.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 12.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 12.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 12.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 12.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 12.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 12.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 12.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 12.1.14 R27 Register (Address = 0x1B) [reset = 0x0000]
      15. 12.1.15 R28 Register (Address = 0x1C) [reset = 0x0000]
      16. 12.1.16 R32 Register (Address = 0x20) [reset = 0x0000]
      17. 12.1.17 R33 Register (Address = 0x21) [reset = 0x0000]
      18. 12.1.18 R146 Register (Address = 0x92) [reset = 0x0000]
      19. 12.1.19 R147 Register (Address = 0x93) [reset = 0x0000]
      20. 12.1.20 R148 Register (Address = 0x94) [reset = 0x0000]
      21. 12.1.21 R238 Register (Address = 0xEE) [reset = 0x0000]
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RER|16
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

VDD = VDDO = 1.8 V, 2.5 V or 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY STABILITY
∆ftotal Total frequency stability –25 25 ppm
∆finit Initial frequency stability TA = 25°C –1 1 ppm
∆ftemp Frequency stability due to temperature Over Recommended Operating Condition, dT/dt < 10°K/min –10 10 ppm
∆faging Frequency stability due to aging 10 years at 25°C TBD TBD ppm
LP-HCSL CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 400 MHz
Vmin Output low voltage (undershoot included) –60 25 mV
Vovershoot Overshoot voltage. Vmax - VOH 150 mV
VOH,2.5/3.3 Output high voltage. VDD = 2.5 V or 3.3 V code = 0 594 625 656 mV
code = 1 614 647 679 mV
code = 2 635 668 702 mV
code = 3 656 690 725 mV
code = 4 676 712 747 mV
code = 5 697 733 770 mV
code = 6 (default) 717 755 793 mV
code = 7 738 777 816 mV
code = 8 758 798 838 mV
code = 9 779 820 861 mV
code = 10 800 842 884 mV
code = 11 820 863 907 mV
code = 12 841 885 929 mV
code = 13 861 907 952 mV
code = 14 882 928 975 mV
code = 15 903 950 998 mV
VOH,1.8 Output high voltage. VDD = 1.8 V code = 0 563 625 688 mV
code = 1 582 647 712 mV
code = 2 601 668 735 mV
code = 3 621 690 759 mV
code = 4 641 712 783 mV
code = 5 660 733 806 mV
code = 6 (default) 680 755 831 mV
code = 7 699 777 855 mV
code = 8 718 798 878 mV
code = 9 738 820 902 mV
code = 10 758 842 926 mV
code = 11 777 863 949 mV
code = 12 797 885 974 mV
code = 13 816 907 998 mV
code = 14 835 928 1021 mV
code = 15 855 950 1045 mV
Zdiff LP-HCSL static differential impedance 80.75 85 91.25 Ω
95 100 105 Ω
dV/dt Output slew rate (rising and falling edge) Measured from –150 mV to +150 mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 0 (TBD)(1) 2.1 3.1 V/ns
Measured from –150 mV to +150 mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 0(1) 2.3 3.5 V/ns
Measured from –150 mV to +150 mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 1(1) 2 3.2 V/ns
Measured from –150 mV to +150 mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 2(1) 1.7 2.8 V/ns
Measured from –150 mV to +150 mV on the differential waveform, centered on the zero crossing point. OUTx_SLEW_RATE = 3(1) 1.4 2.7 V/ns
∆dV/dt Rising edge rate to falling edge rate matching See(1) 3 %
ODC Output duty cycle See(1) 49.9 50.3 %
fout ≤ 325 MHz 48.8 50.8 %
325 MHz < fout ≤ 400 MHz 48.6 51.8 %
tskew Output to output skew Same FOD, LP-HCSL output 50 ps
Vcross Absolute crossing point voltage See(1) 280 480 mV
∆Vcross Variation of Vcross over all clock edges See(1) 30 mV
|VRB| Absolute value of ring back voltage See(1) 100 mV
tstable Time before VRB is allowed See(1) 500 ps
Jcycle-to-cycle Cycle to cycle jitter, Common Clock no SSC See(1) 150 ps
Jcycle-to-cycle Cycle to cycle jitter, Common Clock, -0.5% SSC See(1) 150 ps
tperiod_abs Absolute period including jitter and SSC See(1) 9.949 10 10.101 ns
tperiod_avg_CC Average clock period accuracy, Common Clock See(1) –100 2600 ppm
tperiod_avg_SRIS Average clock period accuracy, SRIS See(1) –100 1600 ppm
LVDS CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 400 MHz
|VOD| Steady-state magnitude of the differnetial output voltage |VOUTP - VOUTN| 100 Ω external termination 250 350 450 mV
∆Vpp-diff Change in differential output voltage swing between complementary output states 100 Ω external termination 50 mV
VOS Output offset voltage (common mode voltage) VDDO = 3.3 V, 100 Ω external termination 1.12 1.2 1.365 V
VDDO = 2.5 V, 100 Ω external termination 1.1 1.2 1.345 V
VDDO = 1.8 V, 100 Ω external termination 0.8 0.97 V
∆VOS Change in VOS between complementary output states 50 mV
ISA, ISB Short-circuit current. Magnitude of current with the generator output terminals short-circuited to the generator circuit common –24 24 mA
ISAB Short-circuit current. Magnitude of current with generator output terminals short-circuited to each other –12 12 mA
tR, tF 20% to 80% differential rise/fall time PADCAP_CHx = 0 195 315 ps
PADCAP_CHx = 1 250 440 ps
PADCAP_CHx = 2 270 610 ps
PADCAP_CHx = 3 280 800 ps
tskew Output to output skew Same FOD, LVDS output 50 ps
ODC Output duty cycle 49 51.1 %
LVCMOS CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 200 MHz
dV/dt Output slew rate VDDO = 3.3 V ± 5%, measured from 20% to 80%, 4.7 pF load 2.6 4.7 V/ns
VDDO = 2.5 V ± 5%, measured from 20% to 80%, 4.7 pF load 2.6 3.7 V/ns
VDDO = 1.8 V ± 5%, measured from 20% to 80%, 4.7 pF load 1 3.2 V/ns
VOH Output high voltage IOH = –15 mA at 3.3 V 0.8 x VDDO VDDO V
IOH = –12 mA at 2.5 V
IOH = –8 mA at 1.8 V
VOL Output low voltage IOL = 15 mA at 3.3 V 0.4 V
IOL = 12 mA at 2.5 V
IOL = 8 mA at 1.8 V
Ileak Output leakage current Output tri-stated. VDD = VDDO = 3.465 V –5 0 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25 MHz 45 55 %
fout > 156.25 MHz 40 60 %
tskew Output-to-output skew Same FOD, LVCMOS output 50 ps
Cload Maximum load capacitance 15 pF
LVCMOS REFCLK CHARATERISTICS
fout Output frequency See(2) 12.5(3) 200 MHz
dV/dt Output slew rate VDDO = 3.3 V ± 5%, measured from 20% to 80%, 4.7 pF load(2) 2.6 6.7 V/ns
VDDO = 2.5 V ± 5%, measured from 20% to 80%, 4.7 pF load(2)(4) 1.8 4.5 V/ns
VDDO = 1.8 V ± 5%, measured from 20% to 80%, 4.7 pF load(2)(4) 1 3.2 V/ns
Ileak Output leakage current Output tri-stated. VDD = VDDO = 3.465 V(2)(4) –5 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25 MHz(2) 45 55 %
ODC Output duty cycle fout > 156.25 MHz(2) 40 60 %
Cload Maximum load capacitance See(2) 15 pF
RJ Random jitter 12 kHz to 20 MHz integrated jitter at 50 MHz(2) 0.5 ps
SSC CHARACTERISTICS
fout Output frequency range that supports SSC (any output format) 2.5 200 MHz
fSSC SSC modulation frequency 30 31.5 33 kHz
fSSC-deviation SSC deviation (modulation depth) Down spread (programmable) –3 –0.1 %
Center spread (programmable) ±0.05 ±1.5 %
fSSC-deviation-accuracy SSC deviation accuracy fout ≤ 100 MHz, down spread 0 0.01 %
100 MHz < fout ≤ 200 MHz, down spread 0 0.05 %
fout ≤ 100 MHz, center spread 0 0.01 %
100 MHz < fout ≤ 200 MHz, center spread 0 0.05 %
df/dt max SSC frequency slew rate 0 < fSSC-deviation ≤ –0.5% 1250 ppm/us
JITTER CHARACTERISTICS
JPCIe1-cc-SSC_off PCIe Gen 1 Common Clock jitter, SSC is off (jitter limit = 86 ps) SSC disabled on both outputs 0.4 ps
JPCIe1-cc-SSC_on PCIe Gen 1 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 86 ps) SSC enabled on both outputs 0.7 ps
JPCIe2-cc-SSC_off PCIe Gen 2 Common Clock jitter, SSC is off (jitter limit = 3 ps) SSC disabled on both outputs 0.1 0.2 ps
JPCIe2-cc-SSC_on PCIe Gen 2 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 3 ps) SSC enabled on both outputs 0.2 0.35 ps
JPCIe2-SRNS PCIe Gen 2 SRNS jitter SSC disabled on both outputs 0.1 0.26 ps
JPCIe2-SRIS PCIe Gen 2 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 0.2 0.36 ps
JPCIe3-cc-SSC_off PCIe Gen 3 Common Clock jitter, SSC is off (jitter limit = 1 ps) SSC disabled on both outputs 32.8 60 fs
JPCIe3-cc-SSC_on PCIe Gen 3 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 1 ps) SSC enabled on both outputs 55.4 109 fs
JPCIe3-SRNS PCIe Gen 3 SRNS jitter SSC disabled on both outputs 35.9 67 fs
JPCIe3-SRIS PCIe Gen 3 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 155.6 317 fs
JPCIe4-cc-SSC_off PCIe Gen 4 Common Clock jitter, SSC is off (jitter limit = 500 fs) SSC disabled on both outputs 32.8 60 fs
JPCIe4-cc-SSC_on PCIe Gen 4 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 500 fs) SSC enabled on both outputs 55.4 110 fs
JPCIe4-SRNS PCIe Gen 4 SRNS jitter SSC disabled on both outputs 35.9 68 fs
JPCIe4-SRIS PCIe Gen 4 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 86.4 164 fs
JPCIe5-cc-SSC_off PCIe Gen 5 Common Clock jitter, SSC is off (jitter limit = 150 fs) SSC disabled on both outputs 11.1 26 fs
JPCIe5-cc-SSC_on PCIe Gen 5 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 150 fs) SSC enabled on both outputs 20.3 47 fs
JPCIe5-SRNS PCIe Gen 5 SRNS jitter SSC disabled on both outputs 12.7 30 fs
JPCIe5-SRIS PCIe Gen 5 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 22.9 51 fs
JPCIe6-cc-SSC_off PCIe Gen 6 Common Clock jitter, SSC is off (jitter limit = 100 fs) SSC disabled on both outputs 7.9 16 fs
JPCIe6-cc-SSC_on PCIe Gen 6 Common Clock jitter, –0.5% ≤ SSC < 0% (jitter limit = 100 fs) SSC enabled on both outputs 13.5 28 fs
JPCIe6-SRNS PCIe Gen 6 SRNS jitter SSC disabled on both outputs 11.2 24 fs
JPCIe6-SRIS PCIe Gen 6 SRIS jitter, –0.3% ≤ SSC < 0% SSC enabled on both outputs 17.7 36 fs
RJRMS 12 kHz to 20 MHz RMS jitter fout = 100 MHz 144 200 fs
RJRMS 12 kHz to 20 MHz RMS jitter fout = 125 MHz 117.6 150 fs
RJRMS 12 kHz to 20 MHz RMS jitter fout = 156.25 MHz 108.5 125 fs
RJRMS 12 kHz to 20 MHz RMS jitter fout = 212.5 MHz 107.3 150 fs
RJRMS 12 kHz to 20 MHz RMS jitter fout = 312.5 MHz 91.9 115 fs
TIMING CHARACTERISTICS
tstartup Start-up time VDD = 2.5 V or 3.3 V. Time elapsed from all VDD pins reach 2.1 V until first output clock rising edge. Output clock is always within specification 1 ms
VDD = 1.8 V. Time elapsed from all VDD pins reach 1.6 V until first output clock rising edge. Output clock is always within specification 1.5 ms
tOE Output enable time.  After CLOCK_READY status is '1', time elapsed between OE assertion and first output clock rising edge. Output is not tristated when disabled. 7 output clock cycles
tOD Output disable time.  Time elapsed between OE deassertion and last output clock falling edge. 7 output clock cycles
POWER CONSUMPTION CHARACTERISTICS
IDD Core supply current, not including output drivers One FOD enabled, 100 MHz ≤ fFOD ≤ 200 MHz 49.1 TBD mA
One FOD enabled, 200 MHz < fFOD ≤ 400 MHz 52.7 TBD mA
Two FODs enabled, 100 MHz ≤ fFOD ≤ 200 MHz 61.7 TBD mA
Two FODs enabled, 200 MHz < fFOD ≤ 400 MHz 68.5 TBD mA
IDDO Output supply current, per output channel LP-HCSL. fout ≤ 100 MHz 10.1 TBD mA
LP-HCSL. 100 MHz < fout ≤ 200 MHz 13.2 TBD mA
LP-HCSL. 200 MHz < fout ≤ 300 MHz 13.7 TBD mA
LP-HCSL. 300 MHz < fout ≤ 400 MHz 14.4 TBD mA
LVDS. fout ≤ 100 MHz 6 TBD mA
LVDS. 100 MHz < fout ≤ 200 MHz 6.8 TBD mA
LVDS. 200 MHz < fout ≤ 300 MHz 7.6 TBD mA
LVDS. 300 MHz < fout ≤ 400 MHz 8.4 TBD mA
1.8 V LVCMOS. fout = 50 MHz 4.2 TBD mA
1.8 V LVCMOS. fout = 200 MHz 11.7 TBD mA
2.5 V LVCMOS. fout = 50 MHz 5.6 TBD mA
2.5 V LVCMOS. fout = 200 MHz 15.3 TBD mA
3.3 V LVCMOS. fout = 50 MHz 6.8 TBD mA
3.3 V LVCMOS. fout = 200 MHz 19.2 TBD mA
IDDREF REFCLK supply current 1.8 V LVCMOS. fout = 50 MHz 3.4 TBD mA
1.8 V LVCMOS. fout = 200 MHz 9.5 TBD mA
2.5 V LVCMOS. fout = 50 MHz 4.7 TBD mA
2.5 V LVCMOS. fout = 200 MHz 12.8 TBD mA
3.3 V LVCMOS. fout = 50 MHz 5.9 TBD mA
3.3 V LVCMOS. fout = 200 MHz 16.6 TBD mA
PSNR CHARACTERISTICS
PSNRLVCMOS Power Supply Noise Rejection for LVCMOS outputs(4) 10 kHz –76.7 –61.2 dBc
50 kHz –80.9 –60.9 dBc
100 kHz –81.8 –60 dBc
500 kHz –84.3 –64.9 dBc
1 MHz –97.6 –82.1 dBc
5 MHz –104.3 –83.1 dBc
10 MHz –108.7 –94.2 dBc
PSNRLVDS Power Supply Noise Rejection for LVDS outputs(4) 10 kHz –79.5 –74.5 dBc
50 kHz –83.5 –77 dBc
100 kHz –83 –75.3 dBc
500 kHz –88.3 –83.1 dBc
1 MHz –123.4 –106.6 dBc
5 MHz –115 –92.3 dBc
10 MHz –123.7 –108.9 dBc
PSNRLP-HCSL Power Supply Noise Rejection for LP-HCSL outputs(4) 10 kHz –80.1 –74.5 dBc
50 kHz –84.7 –76.7 dBc
100 kHz –84.6 –73.7 dBc
500 kHz –93.1 -82.9 dBc
1 MHz –124.6 –106.8 dBc
5 MHz –114.3 –92.9 dBc
10 MHz –123 –109.2 dBc
2-STATE LOGIC INPUT CHARACTERISTICS
VIH-Pin2 Input high voltage for Pin 2 0.7 × VDD VDDD + 0.3 V
VIL-Pin2 Input low voltage for Pin 2 GND – 0.3 0.3 × VDD V
VIH-Pin1 Input high voltage for Pin 1 1.15 VDD + 0.3 V
VIL-Pin1 Input low voltage for Pin 1 –0.3 0.65 V
VIH-Pin3,4 Input voltage high for Pin 3, 4 0.7 × VDD VDD + 0.3 V
VIL-Pin3,4 Input voltage low for Pin 3, 4 GND - 0.3 0.8 V
VIH-Pin15 Input voltage high for Pin 15 0.65 × VDD VDD + 0.3 V
VIL-Pin15 Input voltage low for Pin 15 –0.3 0.4 V
Rint-up/down-Pin1,2 Internal pullup or pulldown resistor for Pin 1 50 75 105 kΩ
Rint-down-Pin3,4,15 Internal pulldown resistor for Pin 2, 3, 4, 15 620 880 1200 kΩ
Rext-up/down-Pin1,2 Recommended external pullup or pulldown resistor for Pin 1, 2 0 1 10 kΩ
Rext-up/down-Pin3,4,15 Recommended external pullup or pulldown resistor for Pin 3, 4, 15 0 10 60 kΩ
tR/tF OE signal rise or fall time 10 ns
Cin Input capacitance 3 pF
ENVIRONMENTAL TESTS
Sinusoidal Vibration-4g Frequency drift under sinusoidal vibration. 4g acceleration. x, y, z direction. 10 Hz TBD ppb/g
20 Hz TBD ppb/g
50 Hz TBD ppb/g
100 Hz TBD ppb/g
200 Hz TBD ppb/g
500 Hz TBD ppb/g
1 kHz TBD ppb/g
2 kHz TBD ppb/g
Sinusoidal Vibration-10g Frequency drift under sinusoidal vibration. 10g acceleration. x, y, z direction. 50 Hz TBD ppb/g
100 Hz TBD ppb/g
200 Hz TBD ppb/g
500 Hz TBD ppb/g
1 kHz TBD ppb/g
2 kHz TBD ppb/g
(1) PCIe test load, 15 dB loss at 4 GHz, fout = 100 MHz, Zdiff = 100 Ω
(2) Tested with 10 kΩ external pullup or pulldown resistor
(3) REFCLK can be /2, /4, /8 from either FOD0 or FOD1. Both FODs support 100 to 400 MHz.
(4) All power supply pins are tied together. 0.1 µF capacitor placed close to each power supply pin. Apply 50 mVpp ripple and measure the spur level at the clock output