The I²C port on the LMK3H0102 works as a peripheral device and supports both the 100-kHz standard mode and 400-kHz fast-mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less than 50-ns duration. The I²C timing requirements are provided in the I2C Interface Specification. Figure 7-9 shows the timing diagram.

Figure 7-9 I²C Timing Diagram

The LMK3H0102 is accessed through a 7-bit peripheral address transmitted as part of an I²C packet. Only the device with a matching peripheral address responds to subsequent I²C commands. In I²C mode, the LMK3H0102 allows up to four unique peripheral devices to occupy the I2C bus based on the pin strapping of FMT_ADDR (tied to VDD, GND, SDA, or SCL). The device peripheral address is 11010xx (the two LSBs are determined by the FMT_ADDR pin).

During the data transfer through the I²C interface, one clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the controller. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit and bytes are sent MSB first. The LMK3H0102 has an 8-bit register address, followed by a 16-bit data word.

The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’ = 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA line high during the 9th clock pulse.

The I²C controller initiates the data transfer by asserting a start condition which initiates a response from all peripheral devices connected to the serial bus. Based on the 8-bit address byte sent by the controller over the SDA line (consisting of the 7-bit peripheral address (MSB first) and an R/W’ bit), the device whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data transfer with the controller.

After the data transfer occurs, stop conditions are established. In write mode, the controller asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the peripheral. In read mode, the controller receives the last data byte from the peripheral but does not pull SDA low during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the peripheral knows the data transfer is finished and enters the idle mode. The controller then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. Figure 7-10 shows a generic I²C transaction. Figure 7-11 and Figure 7-12 show the sequence for block writes and block reads using the LMK3H0102, respectively.

Figure 7-10 Generic Programming Sequence

Figure 7-11 Generic Block Write Sequence

Figure 7-12 Generic Block Read Sequence