JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
In this mode, the configuration pins allow for selection of one of four one-time programmable (OTP) pages, as well as output format selection. I2C is not enabled in this mode, as the I2C pins are repurposed for OTP page selection. Table 7-2 shows the OTP page selected based on the state of the OTP_SEL0 and OTP_SEL1 pins. In OTP mode, the FMT_ADDR pin is ignored by default. This is overridden if R9[8] = 1 is burnt into the OTP in the configuration. Otherwise, the output format is determined by Table 7-3.
OTP_SEL1 Pin | OTP_SEL0 Pin | OTP Page |
---|---|---|
Low | Low | 0 |
Low | High | 1 |
High | Low | 2 |
High | High | 3 |
R9[8] | FMT_ADDR Pin | Output Format |
---|---|---|
0 | X | Set by R6[2:0] / R7[4:2] |
1 | GND | LP-HCSL 100 Ω Termination |
1 | VDD | LP-HCSL 85 Ω Termination |
The EFUSE of the devices is permanently programmed and has R0[0] = 1. If a new configuration is desired, the configuration must be loaded through I2C on each start-up.
The following fields can be unique between the four OTP pages. All other register settings are shared between the OTP pages: