The analog inputs are held with the CONVST rising edge (conversion start) signal. The setup time of CONVST referred to the next CLOCK rising edge (system clock) is 12ns (minimum). The conversion automatically starts with the rising CLOCK edge. Do not issue a rising CONVST edge during a conversion (that is, when BUSY is high).

RD (read data) and CONVST are shorted to minimize necessary software and wiring. The RD signal is triggered by the device on the falling CLOCK edge. Therefore, activate the combined signals with the rising CLOCK edge. The conversion then starts with the subsequent rising CLOCK edge. In modes with only SDOA active, the maximum length of the combined RD and CONVST signal is one clock cycle if half-clock timing is used. These modes are II, IV, SII, and SIV.

If CONVST and RD are combined, make sure CS is low whenever a new conversion starts. However, this condition is not required if RD and CONVST are controlled separately. If the first-in, first-out (FIFO) is used, control CONVST separately from RD.

After completing a conversion, the sample capacitors are automatically precharged to the reference voltage value used to significantly reduce crosstalk among the multiplexed input channels.