SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at AVDD and DVDD supply voltage ranges specified in Recommended Operating Conditions, VREF = 2.5V (internal), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –55℃ to 125℃;
typical values at TA = 25°C, AVDD = 5V, and DVDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IDCL Input leakage current –16 16 nA
CIN Input capacitance CHxxx to AGND 45 pF
CID Differential input capacitance CHxxx to AGND 22.5 pF
DC PERFORMANCE
Resolution No missing codes 16 Bits
DNL Differential nonlinearity Half-clock mode –2 ±0.6 2 LSB
Full-clock mode –2 ±0.8 4
INL Integral nonlinearity Half-clock mode –4 ±1.2 4 LSB
Full-clock mode –5 ±1.5 5
VOS Input offset error –2.5 ±0.2 2.5 mV
VOS match ADC to ADC –1.5 ±0.1 1.5 mV
dVOS/dT Input offset error thermal drift 1 µV/℃
GERR Gain error –0.15 0.01 0.15 %FSR
GERR match ADC to ADC –0.15 0.01 0.15 %FSR
GERR/dT GERR thermal drift 1 ppm/℃
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio VIN = 5VPP, fIN = 10kHz 88 92 dB
SNR Signal-to-noise ratio VIN = 5VPP, fIN = 10kHz 89 93 dB
THD Total harmonic distortion VIN = 5VPP, fIN = 10kHz –98 –90 dB
SFDR Spurious-free dynamic range VIN = 5VPP, fIN = 10kHz 89 100 dB
CMRR Common-mode rejection ratio Both ADCs, fIN = dc to 100kHz 92 dB
PSRR Power-supply rejection ratio 75 dB
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range 2.485 2.5 2.525 V
IREF Reference input current 50
CREF External decoupling capacitor 22 µF
INTERNAL VOLTAGE REFERENCE
Reference output DAC resolution 10 Bits
VREFOUT Reference output voltage >20% to 100% of DAC range 0.2 x VREFOUT VREFOUT V
REFIO1, DAC = 3FFh 2.485 2.500 2.515
REFIO2, DAC = 3FFh 2.485 2.500 2.515
DNLDAC DAC DNL –5 ±1 5 LSB
INLDAC DAC INL –5 ±0.5 5 LSB
PSRRDAC Power-supply rejection ratio 73 dB
IREFOUT Output DC current ±2 mA
IREFSC Output short-circuit current(1) 50 mA
DIGITAL INPUTS
Input current(2) VIN = DVDD to DGND –50 50 nA
Digital input capacitance 5 pF
Logic family CMOS with Schmitt Trigger
VIH Input high logic level DVDD = 4.5V to 5.5V 0.7 x DVDD DVDD + 0.3 V
VIL Input low logic level DVDD = 4.5V to 5.5V –0.3 0.3 x DVDD V
Logic family LVCMOS
VIH Input high logic level DVDD = 2.3V to 3.6V 2 DVDD + 0.3 V
VIL Input low logic level DVDD = 2.3V to 3.6V –0.3 0.8 V
DIGITAL OUTPUTS
COUT Output capacitance 5 pF
CLOAD Load capacitance 30 pF
Logic family CMOS
VIH Output high logic level DVDD = 4.5V, ILOAD = –100uA 4.44 V
VIL Output low logic level DVDD = 4.5V, ILOAD = 100uA 0.5 V
Logic family LVCMOS
VIH Output high logic level DVDD = 2.3V, ILOAD = –100uA DVDD – 0.2 V
VIL Output low logic level DVDD = 2.3V, ILOAD = 100uA 0.2 V
POWER SUPPLY
AIDD Analog supply current AVDD = 3.6V 12 18 mA
AVDD = 5.5V 15 25
AVDD = 3.6V, sleep and auto-sleep modes 0.8 2
AVDD = 5.5V, sleep and auto-sleep modes 0.9 6.2
Power-down mode 0.15
DIDD Digital supply current DVDD = 3.6V, CLOAD = 10pF 1.1 3 mA
DVDD = 5.5V, CLOAD = 10pF 3 13
PD Power-dissipation
(normal operation)		 AVDD = DVDD = 3.6V 47.2 66.6 mW
AVDD = 5.5V, DVDD = 3.6V 86.5 135
(1) Reference output current is not internally limited.
(2) Digital pins input and output characteristics specified by design; not production tested.