SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

ADC168M102R-SEP RHB Package,32-Pin VQFN(Top View) Figure 4-1 RHB Package,32-Pin VQFN(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 12, 30 P Analog ground. Connect to analog ground plane.
AVDD 13, 29 P Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1μF ceramic capacitor.
BUSY 23 DO Converter busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the conversion is complete.
CHA0N/CHA0 8 AI Fully differential inverting analog input channel A1 or pseudo-differential input A0
CHA0P/CHA1 7 AI Fully differential noninverting analog input channel A1 or pseudo-differential input A1
CHA1N/CHA2 6 AI Fully differential inverting analog input channel A1 or pseudo-differential input A2
CHA1P/CHA3 5 AI Fully differential noninverting analog input channel A1 or pseudo-differential input A3
CHB0N/CHB0 4 AI Fully differential inverting analog input channel B0 or pseudo-differential input B0
CHB0P/CHB1 3 AI Fully differential noninverting analog input channel B0 or pseudo-differential input B1
CHB1N/CHB2 2 AI Fully differential inverting analog input channel B1 or pseudo-differential input B2
CHB1P/CHB3 1 AI Fully differential noninverting analog input channel B1 or pseudo-differential input B3
CLOCK 22 DI External clock input. The range is 0.5MHz to 20MHz in half-clock mode, or 1MHz to 40MHz in full-clock mode.
CMA 31 AI Common-mode voltage input for channels Ax (in pseudo-differential mode only).
CMB 32 AI Common-mode voltage input for channels Bx (in pseudo-differential mode only).
CONVST 19 DI Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST. Thereafter, the conversion starts with the next rising edge of the CLOCK pin.
CS 21 DI Chip select. When this pin is low, the SDOx, SDI, and RD pins are active. When this pin is high, the SDOx outputs are tri-stated, and the SDI and RD inputs are ignored.
DGND 28 P Digital ground. Connect to digital ground plane.
DVDD 27 P Digital supply, 2.3V to 5.5V. Decouple to DGND with a 1μF ceramic capacitor.
M0 17 DI Mode pin 0. Selects analog input channel mode (see Table 6-5).
M1 16 DI Mode pin 1. Selects the digital output mode (see Table 6-5).
NC 14, 15, 26 NC This pin is not internally connected.
RD 20 DI Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
REFIO1 9 AIO Reference voltage input/output 1. Connect 22µF ceramic capacitor is connected to RGND.
REFIO2 10 AIO Reference voltage input/output 2. Connect 22µF ceramic capacitor is connected to RGND.
RGND 11 P Reference ground. Connect this pin to analog ground plane with a dedicated via.
SDI 18 DI Serial data input. This pin sets up the internal registers. The data on SDI are ignored when CS is high.
SDOA 25 DO Serial data output for converter A. This pin is in tri-state when CS is high.
SDOB 24 DO Serial data output for converter B. Active only if M1 is low. This pin is in tri-state when CS is high.
(1) AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output, P = power supply, NC = not connected.