SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.1.6 REFIOx

The ADC168M102R-SEP includes a low-drift, 2.5V internal reference source. This source feeds two, 10-bit string DACs that are controlled through registers. As a result of this architecture, the reference voltages at REFIOx are programmable in 2.44mV steps and adjusted to application requirements without additional external components. The actual output voltage is calculated using Equation 3, with code being the decimal value of the REFDACx register content:

Equation 3. ADC168M102R-SEP

The reference DAC has a fixed transition at code 508 (0x1FC). At this code, the DAC shows a jump of up to 10mV in the transfer function. Table 6-3 lists some examples of internal reference DAC settings. However, to provide proper performance, do not program the REFDACx output voltage below 0.5V.

Table 6-3 REFDACx Setting Examples
VREFOUT (NOM)DECIMAL CODEBINARY CODEHEXADECIMAL
CODE
0.5000V20500 1100 11010CDh
1.2429V50701 1111 11001FBh
1.2427V50801 1111 11011FCh
2.5000V102311 1111 11113FFh

A minimum of 22μF capacitance is required on each REFIOx output to keep the references stable. The settling time is 8ms (maximum) with the reference capacitor connected. Smaller reference capacitance values reduce the DNL, INL, and ac performance of the device. By default, both reference outputs are disabled and the respective values are set to 2.5V after power-up.

For applications that use an external reference source, the internal reference is disabled (default) using the RPD bit in the CONFIG register (see the Digital section). The REFIOx pins are directly connected to the ADC; therefore, the internal switching generates spikes at this pin. Thus, use an external 22µF capacitor to the analog ground (AGND) to stabilize the reference input voltage.

Leave disabled REFIOx pins floating or directly tied to AGND or RGND.

Each reference DAC output is individually selected as a source for each channel input using the Rxx bits in the REFCM register. Figure 6-3 shows a simplified block diagram of the internal circuit.

ADC168M102R-SEP Reference Selection CircuitFigure 6-3 Reference Selection Circuit