SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.1.1 Analog Inputs

As shown in Figure 6-1, each ADC is fed by an input multiplexer. Each multiplexer is used in either a fully differential 2:1 configuration (Table 6-1) or a pseudo-differential 4:1 configuration (Table 6-2).

ADC168M102R-SEP Input Multiplexer ConfigurationFigure 6-1 Input Multiplexer Configuration

Use either the external M0 pin or the C[1:0] bits in the Configuration (CONFIG) register for channel selection in fully differential mode. In pseudo-differential mode, channel selection is performed with the SEQFIFO register. In either mode, changing the multiplexer settings impacts the conversion started with the next CONVST pulse.

Table 6-1 Fully Differential 2:1 Multiplexer Configuration
C1 C0 ADC+ ADC–
0 x CHx0P CHx0N
1 x CHx1P CHx1N
Table 6-2 Pseudo-Differential 4:1 Multiplexer Configuration
C1 C0 ADC+ ADC–
0 0 CHx0 CMx/REFIOx
0 1 CHx1 CMx/REFIOx
1 0 CHx2 CMx/REFIOx
1 1 CHx3 CMx/REFIOx

The input path for the converter is fully differential and provides a good common-mode rejection of 92dB at 100kHz. The high CMRR also helps suppress noise in harsh industrial environments.

Each 40pF sample-and-hold capacitor (CS in Figure 6-2) is connected through switches to the multiplexer output. Opening the switches holds the sampled data during the conversion process. After the conversion completes, both capacitors are precharged for the duration of one clock cycle to the voltage present at the REFIOx pin. After precharging, the multiplexer outputs are connected to the sampling capacitors again. The voltage at the analog input pin is usually different from the reference voltage. Therefore, charge the sample capacitors to within one-half LSB for 16-bit accuracy during the acquisition time tACQ (see Figure 5-1 and Figure 5-2).

ADC168M102R-SEP Equivalent Analog Input CircuitFigure 6-2 Equivalent Analog Input Circuit

Acquisition is indicated with the BUSY signal low. Acquisition starts by closing the input switches (after finishing the previous conversion and precharging) and finishes with the rising edge of the CONVST signal. If the device operates at full speed, the acquisition time is typically 100ns.

As shown in, Equation 1 calculate the minimum –3dB bandwidth of the driving operational amplifier with n = 16 for the resolution of the ADC168M102R-SEP:

Equation 1. ADC168M102R-SEP

With tACQ = 100ns, the minimum bandwidth of the driving amplifier is 19MHz for the ADC168M102R-SEP. The required bandwidth is potentially lower if the application allows a longer acquisition time.

A gain error occurs if a given application does not fulfill the settling requirement in Equation 1. However, linearity and THD are not directly affected as a result of precharging the capacitors.

The OPA365 from Texas Instruments is recommended as a driver. In addition to offering the required bandwidth, the OPA365 also provides a low offset and excellent THD performance (see the Application and Implementation section).

The phase margin of the driving operational amplifier is usually reduced by the ADC sampling capacitor. A resistor placed between the capacitor and the amplifier limits this effect. Therefore, place an internal 100Ω resistor (RSER) in series with the switch. The switch resistance (RSW) is typically 100Ω; see Figure 6-2).

An input driver is not required if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2:

Equation 2. ADC168M102R-SEP

where:

  • n = 16 is the ADC168M102R-SEP resolution
  • CS = 40pF sample capacitance
  • RSER = 100Ω input resistor value
  • RSW = 100Ω switch resistance value

With tACQ = 100ns, make sure the maximum source impedance is less than 12Ω for the ADC168M102R-SEP. The source impedance is potentially higher if the ADC is used at a lower data rate.

The differential input voltage range of the ADC is ±VREF, the voltage at the selected REFIOx pin.

Keep the voltage for all inputs within the 0.3V limit below AGND and above AVDD. Do not allow dc current to flow through the inputs. Exceeding these limits causes the internal ESD diodes to conduct, leading to increased leakage current that potentially damages the device. Current is only necessary to recharge the sample-and-hold capacitors.

Directly tie any unused inputs to AGND or RGND without the need of a pulldown resistor.