SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5.2.2 Mode II (Half-Clock Mode Only)

With M0 = 0 and M1 = 1, the ADC168M102R-SEP also operates in manual channel-control mode. In this mode, the device outputs data on the SDOA pin only when SDOB is set to high impedance. All other pins function in the same manner as in mode I.

In half-clock mode, the device requires 2μs to perform a complete read cycle. This requirement is because 40 clock cycles are needed to output the results from both ADCs (instead of 20 cycles if M1 = 0). As shown in Figure 6-6, if the CONVST signal is issued every 1.0μs (required for the RD signal) as in mode I, ignore every second pulse. Make sure the CONVST and RD signals are not be longer than one clock cycle to provide proper functionality and avoid output data corruption.

Full-clock mode is not supported in this operational mode.

The output data consist of a 0, an ADC indicator, and 16 bits of conversion result with any trailing zeroes. The ADC indicator is 0 for CHAx or 1 for CHBx.

This mode is used for fully- or pseudo-differential inputs. Channel information is valid in fully differential mode only if CID is 0. CID contains correct ADC information when the channel bit is invalid in pseudo-differential mode. The FIFO is not available in this mode.

Changes to the FE, SR, PDE, and CID register bits are active starting from the next conversion with a delay of one read access.

Update the register settings using every other RD pulse. As shown in Figure 6-6, align these pulses either with the one starting the conversion or the one to read the conversion results of channel B.

ADC168M102R-SEP Mode II Timing (M0 = 0, M1 = 1, PDE = 0, CID = 0, Pseudo-Differential Example) Figure 6-6 Mode II Timing (M0 = 0, M1 = 1, PDE = 0, CID = 0, Pseudo-Differential Example)