SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

at AVDD and DVDD supply voltage ranges specified in Recommended Operating Conditions, VREF = 2.5V (internal), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –55℃ to 125℃;
typical values at TA = 25°C, AVDD = 5V, and DVDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
tCONV Conversion time per ADC Half-clock mode 17.5 tCLK
Full-clock mode 35
tACQ Acquisition time Half-clock mode 2 tCLK
Full-clock mode 4
tA Aperture delay 6 ns
tA match 50 ps
Aperture jitter 50 ps
SPI INTERFACE TIMINGS
tD1 CONVST rising edge to BUSY high delay(1) 2.3V ≤ DVDD ≤ 3.6V 19 ns
4.5V ≤ DVDD ≤ 5.5V 16
tD2 CLOCK 18th falling edge (half-clock mode) or 24th rising edge (full-clock mode) to BUSY low delay 2.3V ≤ DVDD ≤ 3.6V 25 ns
4.5V ≤ DVDD ≤ 5.5V 20
tD3 CLOCK rising edge to next data valid delay in half-clock mode 2.3V ≤ DVDD ≤ 3.6V 14 ns
4.5V ≤ DVDD ≤ 5.5V 12
tH3 Output data to CLOCK rising edge hold time, half-clock mode 3 ns
tD4 CLOCK falling edge to next data valid delay, full-clock mode 19 ns
tH4 Output data to CLOCK falling edge hold time, full-clock mode 7 ns
tD5 RD falling edge to first data valid 2.3V ≤ DVDD ≤ 3.6V 16 ns
4.5V ≤ DVDD ≤ 5.5V 12 ns
tD6 CS rising edge to SDOx tristate delay 6 ns
INTERNAL VOLTAGE REFERENCE
tREFON Reference output settling time CREF = 22µF 8 ms
(1) Not applicable in auto-sleep power-down mode.