SNAS849A December   2024  – July 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples
    2. 10.2 Package Option Addendum
    3. 10.3 Tape and Reel Information

6.3.7.1 VCO Calibration

To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency range is divided into several different frequency bands. The entire range, 7500MHz to 15000MHz, covers an octave that allows the divider to take care of frequencies below the lower bound. This creates the need for frequency calibration to determine the correct frequency band given a desired output frequency. The frequency calibration routine is activated any time that the R0 register is programmed with the FCAL_EN = 1 or toggle CAL pin from low-to-high in Pin-mode. A valid OSCin signal must present before VCO calibration begins.

The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated any time the R0 register is programmed.

The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much without being re-calibrated, some minor phase noise degradation can result. The maximum allowable drift for continuous lock, ΔTCL, is stated in the electrical specifications. For this device, temperature of 125°C means the device never loses lock if the device is operated within this range.

The LMX2624-SP allows the user to assist the VCO calibration. In general, there are three kinds of assistance, as shown in Table 6-4. Refer to the application note for detailed implementation procedures and performance demonstrations of VCO calibration technique showcased for commercial devices.

Table 6-4 Assisting the VCO Calibration Speed
ASSISTANCE LEVEL DESCRIPTION VCO_SEL VCO_SEL_FORCE
VCO_CAPCTRL_FORCE
VCO_DACISET_FORCE		 VCO_CAPCTRL
VCO_DACISET
No assist User does nothing to improve VCO calibration speed. 7 0 Don't Care
Partial assist Upon every frequency change, before the FCAL_EN bit is checked, the user provides the initial starting VCO_SEL Select by table 0 Don't Care
Full assist The user forces the VCO core (VCO_SEL), amplitude settings (VCO_DACISET), and frequency band (VCO_CAPCTRL) and manually sets the value. If the two frequency points are no more than 5MHz apart and on the same VCO core, the user can set the VCO amplitude and capcode for any frequency between those two points using linear interpolation Select by readback 1 Select by readback

For the no assist method, just set VCO_SEL=7 and this is done. For partial assist, the VCO calibration speed can be improved by changing the VCO_SEL bit according to the frequency. Note that the frequency is not the actual VCO core range, but favors selecting the VCO. This is not only optimal for VCO calibration speed, but required for reliable locking.

Table 6-5 Minimum VCO_SEL for Partial Assist
fVCO VCO CORE (MIN)
7500 - 8600MHz VCO1
8600 - 9900MHz VCO2
9900 - 10800MHz VCO3
10800 -11900MHz VCO4
11900 - 13000MHz VCO5
13000 - 14000MHz VCO6
14000 - 15000MHz VCO7

For fastest calibration time, use the minimum VCO core as recommended in the previous table. The following table shows typical VCO calibration times with or without analog lock time for this choice in bold as well as showing how long the calibration time is increased if a higher than necessary VCO core is chosen. Realize that these calibration times are specific to these fOSC and fPD conditions specified and at the boundary of two cores, sometimes the calibration time can be increased.

Table 6-6 Typical Calibration Times (µs) Without Analog Lock Time for fOSC = 100MHz, fPD = 200MHz and fSM = 50MHz
fVCO VCO_SEL
VCO7 VCO6 VCO5 VCO4 VCO3 VCO2 VCO1
8.1GHz 650 614 620 376 256 243 191
9.3GHz 606 589 587 335 196 177 Invalid
10.4GHz 598 579 570 338 177 Invalid
11.4GHz 543 540 530 284 Invalid
12.5GHz 396 346 300 Invalid
13.6GHz 262 218 Invalid
14.7GHz 164 Invalid
Table 6-7 Typical Calibration Times (µs) With Analog Lock Time for fOSC = 100MHz, fPD = 200MHz and fSM = 50MHz
fVCO VCO_SEL(1)
VCO7 VCO6 VCO5 VCO4 VCO3 VCO2 VCO1
8.1GHz 854 828 822 579 451 437 393
9.3GHz 819 800 794 551 401 380 Invalid
10.4GHz 808 786 781 551 388 Invalid
11.4GHz 767 745 743 494 Invalid
12.5GHz 603 560 513 Invalid
13.6GHz 469 426 Invalid
14.7GHz 385 Invalid
(1) This include Analog lock time for typical loop bandwidth (300kHz).