SNAS849 December   2024 LMX2624-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

5.5 Electrical Characteristics

3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤ +125°C., OSCIN = 100MHz, SM Clock = 12.5MHz,  Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current (VCO output) OUTBUFFA_PD = 0, OUTBUFFB_PD = 1
OUTBUFFA_MUXSEL = 1
OUTBUFFA_DACCTRL = 7, CPG = 7
fOSC = fPD = 100 MHz, fVCO = fOUT = 14.5 GHz		 480 mA
ICC Supply current (channel divider output) OUTBUFFA_PD = 0, OUTBUFFB_PD = 1
OUTBUFFA_MUXSEL = 0 
OUTBUFFA_DACCTRL = 7, CPG = 7
fOSC = fPD = 100 MHz, fVCO = 15Ghz, fOUT = 7 GHz		 640 mA
ICC Supply current (Doubler output) OUTBUFFA_PD = 0, OUTBUFFB_PD = 1
OUTA_MUX = 2 
OUTBUFFA_DACCTRL=7, CPG = 7
fOSC = fPD = 100 MHz, fVCO = 12GHz
fOUT = 24 GHz		 630 mA
ICC Supply current (Doubler output on both RFOUTA and RFOUTB) OUTBUFFA_PD = 0, OUTBUFFB_PD = 0
OUTA_MUX = 2 
OUTBUFFA_DACCTRL=7, CPG = 7
fOSC = fPD = 100 MHz, fVCO = 12GHz
fOUT = 24 GHz		 TBD mA
ICC Power on reset current RESET = 1 (Device wake-up) RESET = 1 (Device wake-up) RESET = 1 (Device wake-up) 289 mA
ICC Power down current POWERDOWN = 1 POWERDOWN = 1 POWERDOWN = 1 14 mA
OUTPUT CHARACTERISTICS
Fout RF output frequency 5 28000 MHz
pOUT Differential output power
OUTx_PWR = 31		 fOUT = 28 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31		 fOUT = 28 GHz 3 dBm
pOUT Differential output power
OUTx_PWR = 31		 fOUT = 26 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31		 fOUT = 26 GHz 2 dBm
pOUT Differential output power
OUTx_PWR = 31		 fOUT = 24 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31		 fOUT = 24 GHz 2 dBm
pOUT Differential output power
OUTx_PWR = 31		 fOUT = 22 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31		 fOUT = 22 GHz 2 dBm
pOUT Differential output power
OUTx_PWR = 31		 fOUT = 18 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31		 fOUT = 18 GHz 3 dBm
pOUT Differential output power
OUTx_PWR = 31; VCO output		 fOUT = 15 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31; VCO output		 fOUT = 15 GHz 3 dBm
pOUT Differential output power
OUTx_PWR = 31; VCO output		 fOUT = 7.5 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31; VCO output		 fOUT = 7.5GHz 7 dBm
pOUT Differential output power
OUTx_PWR = 31; VCO output		 fOUT = 4 GHz TBD dBm
pOUT Single-ended output power(2)(4)
OUTx_PWR = 31; VCO output		 fOUT = 4 GHz 6 dBm
H3/2 1/2 Harmonic, single ended measurement Fout = 2 x Fvco =  24 GHz Measured at 12GHz frequency; TBD dBc
H3/2 1/2 Harmonic, differential ended Fout = 2 x Fvco =  24 GHz Measured at 12GHz frequency; -55 dBc
H3/2 3/2 Harmonic, single ended measurement Fout = 2 x Fvco =  16 GHz Measured at 24GHz frequency TBD dBc
H3/2 3/2 Harmonic, differential ended measurement Fout = 2 x Fvco =  16 GHz Measured at 24GHz frequency TBD dBc
Pmute Single-ended output power leakage when output is muted Fout = 24 GHz -50 dBm
Pmute Single-ended output power leakage when output is muted Fout = 12 GHz -51 dBm
Pmute Single-ended output power leakage when output is muted Fout = 6 GHz -91 dBm
tMUTE Mute enable time Fout = 12 GHz 200 ns
tUNMUTE Mute disable time Fout = 12 GHz 200 ns
isoCH Channel to channel isolation (Doubler to VCO) RFOUTA = 24 GHz; RFOUTB = 12 GHz -39 dBC
isoCH Channel to channel isolation (VCO to CH divider) RFOUTA = 12 GHz; RFOUTB = 6 GHz -53 dBC
isoCH Channel to channel isolation (Doubler to CH divider) RFOUTA = 24 GHz; RFOUTB = 6 GHz -41 dBC
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 1 KHz -87 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 10 KHz -99 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 100 KHz -101 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 1 MHz -113 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 10 MHz -137 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 24 GHz 100 MHz -151 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 1 KHz -97 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 10 KHz -104 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 100 KHz -104 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 1 MHz -117 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 10 MHz -140 dBc/Hz
Phase Noise RF Output Frequency Phase Noise Fout = 15 GHz 100 MHz -156 dBc/Hz
Jitter RMS Jitter Fout = 24 GHz, Integration range 1 KHz to 100 MHz 56 fs
Jitter RMS Jitter Fout = 24 GHz, Integration range 1 KHz to 12 GHz; No filter in clock output TBD fs
Skew Skew between RFOUTA and RFOUTB RFOUTA = RFOUTB = 4GHz 7 ps
INPUT SIGNAL PATH
fOSCin Reference input frequency OSC_2X = 0 OSC_2X = 0 OSC_2X = 0 5 1200 MHz
fOSCin Reference input frequency OSC_2X = 1 OSC_2X = 1 OSC_2X = 1 5 200
vOSCin Reference input voltage Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50 Ω resistor fOSCin ≥ 20 MHz 0.4 2 VPP
vOSCin Reference input voltage Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50 Ω resistor 10 MHz ≤ fOSCin < 20 MHz 0.8 2 VPP
vOSCin Reference input voltage Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50 Ω resistor 5 MHz ≤ fOSCin < 10 MHz 1.6 2 VPP
PHASE DETECTOR AND CHARGE PUMP
fPD Phase detector frequency(1) MASH_ORDER = 0 MASH_ORDER = 0 MASH_ORDER = 0 0.125 250 MHz
fPD Phase detector frequency(1) MASH_ORDER > 0 MASH_ORDER > 0 MASH_ORDER > 0 5 200 MHz
ICPout Charge-pump leakage current CPG = 0 CPG = 0 CPG = 0 15 nA
ICPout Effective charge pump current. This is the sum of the up and down currents CPG = 4 CPG = 4 CPG = 4 3 mA
ICPout Effective charge pump current. This is the sum of the up and down currents CPG = 1 CPG = 1 CPG = 1 6 mA
ICPout Effective charge pump current. This is the sum of the up and down currents CPG = 5 CPG = 5 CPG = 5 9 mA
ICPout Effective charge pump current. This is the sum of the up and down currents CPG = 3 CPG = 3 CPG = 3 12 mA
ICPout Effective charge pump current. This is the sum of the up and down currents CPG = 7 CPG = 7 CPG = 7 15 mA
PNPLL_1/f Normalized PLL 1/f noise fPD = 100 MHz, fVCO = 12 GHz(3) fPD = 100 MHz, fVCO = 12 GHz(3) fPD = 100 MHz, fVCO = 12 GHz(3) –129 dBc/Hz
PNPLL_FOM Normalized PLL noise floor fPD = 100 MHz, fVCO = 12 GHz(3) fPD = 100 MHz, fVCO = 12 GHz(3) fPD = 100 MHz, fVCO = 12 GHz(3) –236 dBc/Hz
VCO CHARACTERISTICS
fVCO VCO frequency 7500 15000 MHz
PNVCO VCO phase noise VCO1
fVCO = 8.1 GHz		 VCO1
fVCO = 8.1 GHz		 100 kHz −105 dBc/Hz
PNVCO VCO phase noise VCO1
fVCO = 8.1 GHz		 VCO1
fVCO = 8.1 GHz		 1 MHz −127 dBc/Hz
PNVCO VCO phase noise VCO1
fVCO = 8.1 GHz		 VCO1
fVCO = 8.1 GHz		 10 MHz −148 dBc/Hz
PNVCO VCO phase noise VCO1
fVCO = 8.1 GHz		 VCO1
fVCO = 8.1 GHz		 100 MHz −155 dBc/Hz
PNVCO VCO phase noise VCO2
fVCO = 9.3 GHz		 VCO2
fVCO = 9.3 GHz		 100 kHz −103 dBc/Hz
PNVCO VCO phase noise VCO2
fVCO = 9.3 GHz		 VCO2
fVCO = 9.3 GHz		 1 MHz −125 dBc/Hz
PNVCO VCO phase noise VCO2
fVCO = 9.3 GHz		 VCO2
fVCO = 9.3 GHz		 10 MHz −146 dBc/Hz
PNVCO VCO phase noise VCO2
fVCO = 9.3 GHz		 VCO2
fVCO = 9.3 GHz		 100 MHz −153 dBc/Hz
PNVCO VCO phase noise VCO3
fVCO = 10.4 GHz		 VCO3
fVCO = 10.4 GHz		 100 kHz −103 dBc/Hz
PNVCO VCO phase noise VCO3
fVCO = 10.4 GHz		 VCO3
fVCO = 10.4 GHz		 1 MHz −125 dBc/Hz
PNVCO VCO phase noise VCO3
fVCO = 10.4 GHz		 VCO3
fVCO = 10.4 GHz		 10 MHz −147 dBc/Hz
PNVCO VCO phase noise VCO3
fVCO = 10.4 GHz		 VCO3
fVCO = 10.4 GHz		 100 MHz −158 dBc/Hz
PNVCO VCO phase noise VCO4
fVCO = 11.4 GHz		 VCO4
fVCO = 11.4 GHz		 100 kHz −101 dBc/Hz
PNVCO VCO phase noise VCO4
fVCO = 11.4 GHz		 VCO4
fVCO = 11.4 GHz		 1 MHz −124 dBc/Hz
PNVCO VCO phase noise VCO4
fVCO = 11.4 GHz		 VCO4
fVCO = 11.4 GHz		 10 MHz −146 dBc/Hz
PNVCO VCO phase noise VCO4
fVCO = 11.4 GHz		 VCO4
fVCO = 11.4 GHz		 100 MHz −158 dBc/Hz
PNVCO VCO phase noise VCO5
fVCO = 12.5 GHz		 VCO5
fVCO = 12.5 GHz		 100 kHz −102 dBc/Hz
PNVCO VCO phase noise VCO5
fVCO = 12.5 GHz		 VCO5
fVCO = 12.5 GHz		 1 MHz −126 dBc/Hz
PNVCO VCO phase noise VCO5
fVCO = 12.5 GHz		 VCO5
fVCO = 12.5 GHz		 10 MHz −147 dBc/Hz
PNVCO VCO phase noise VCO5
fVCO = 12.5 GHz		 VCO5
fVCO = 12.5 GHz		 100 MHz −156 dBc/Hz
PNVCO VCO phase noise VCO6
fVCO = 13.6 GHz		 VCO6
fVCO = 13.6 GHz		 100 kHz −101 dBc/Hz
PNVCO VCO phase noise VCO6
fVCO = 13.6 GHz		 VCO6
fVCO = 13.6 GHz		 1 MHz −124 dBc/Hz
PNVCO VCO phase noise VCO6
fVCO = 13.6 GHz		 VCO6
fVCO = 13.6 GHz		 10 MHz −146 dBc/Hz
PNVCO VCO phase noise VCO6
fVCO = 13.6 GHz		 VCO6
fVCO = 13.6 GHz		 100 MHz −160 dBc/Hz
PNVCO VCO phase noise VCO7
fVCO = 14.7 GHz		 VCO7
fVCO = 14.7 GHz		 100 kHz −101 dBc/Hz
PNVCO VCO phase noise VCO7
fVCO = 14.7 GHz		 VCO7
fVCO = 14.7 GHz		 1 MHz −124 dBc/Hz
PNVCO VCO phase noise VCO7
fVCO = 14.7 GHz		 VCO7
fVCO = 14.7 GHz		 10 MHz −146 dBc/Hz
PNVCO VCO phase noise VCO7
fVCO = 14.7 GHz		 VCO7
fVCO = 14.7 GHz		 100 MHz −157 dBc/Hz
Lock time No Assist mode;  RFOUTA from 9.5GHz to 9.52GHz;Loop Bandwidth = 300KHz, PFD Frequency = 100MHz; 3000 µs
Lock time  Full Assist mode, Loop Bandwidth = 300KHz, PFD Frequency = 100MHz; RFOUTA from 9.5GHz to 9.52GHz, 1PPM settling around RFOUT 16 µs
KVCO VCO Gain 8.1 GHz 94 MHz/V
KVCO VCO Gain 9.3 GHz 106 MHz/V
KVCO VCO Gain 10.4 GHz 122 MHz/V
KVCO VCO Gain 11.4 GHz 148 MHz/V
KVCO VCO Gain 12.5 GHz 185 MHz/V
KVCO VCO Gain 13.6 GHz 202 MHz/V
KVCO VCO Gain 14.7 GHz 233 MHz/V
|ΔTCL| Allowable temperature drift when VCO is not re-calibrated configured in SPI mode 125 °C
H2 VCO second harmonic fVCO = 8 GHz, divider disabled –30 dBc
H3 VCO third harmonic fVCO = 8 GHz, divider disabled −25 dBc
DIGITAL INTERFACE (Applies to SCK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq)
VIH High-level input voltage 1.6 V
VIL Low-level input voltage 0.4 V
IIH High-level input current –100 100 µA
IIL Low-level input current –100 100 µA
VOH High-level output voltage MUXout pin Load current = –5 mA VCC – 0.6 V
VOL Low-level output voltage MUXout pin Load current = 5 mA 0.6 V
SYSREF Output Common mode voltage TBD V
SYREF Output Swing TBD V
SYSREF Frequency range TBD MHz
SYSREF delay step size TBD ps
VL CDIV0, CDIV1, CDIV2 Voltage levels 0 0.4 V
VML CDIV0, CDIV1, CDIV2 Voltage levels 0.8 VCC/3 1.4 V
VMH CDIV0, CDIV1, CDIV2 Voltage levels 1.9 2*VCC/3 2.5 V
VH CDIV0, CDIV1, CDIV2 Voltage levels 3 VCC 3.45 V
VL NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 0 0.4 V
VML NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 0.8 VCC/3 1.4 V
VMH NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 1.9 2*VCC/3 2.5 V
VH NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 3 VCC 3.45 V
(1) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.
(2) Single-ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50-Ω load.
(3) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20× log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_1/f + 20 × log(Fvco / 1GHz) – 10× log(offset / 10kHz). After these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10 PLL_Flat / 10 + 10 PLL_flicker /10 )
(4) Output power, spurs, and harmonics can vary based on board layout and components.