SNAS849 December   2024 LMX2624-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

6.3.14 Treatment of Unused Pins

This device has several pins for many features and there is a preferred way to treat these pins if not needed. For the input pins, a series resistor is recommend but can be directly shorted.

Table 6-14 Recommended Treatment of Pins
PinsSPI ModePin ModeRecommended Treatment if NOT Used
CDIV0, CDIV1, CDIV2Always usedAlways UsedSPI-mode: CDIV0, CDIV1, CDIV2 pins must be GND with 1 kΩ resistor.

Pin-mode: CDIV0, CDVI1, CDVI2 pins must have value other than the GND for all pins at a time. Based on the value on these pins, output Divider is set.

NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Never used Always Used GND with 1 kΩ
CALNever UsedSometimes UsedVCC with 1 kΩ
SYNC, SysRefReqSometimes UsedNever UsedGND with 1 kΩ
OSCinP,OSCinMAlways UsedAlways UsedGND with 50 Ω to ground after the AC-coupling capacitor. If one side of complimentary side is used and other side is not, impedance looking out must be similar for both of these pins.
SCK, SDIAlways UsedNever UsedGND with 1 kΩ
CSBAlways UsedNever UsedVCC with 1 kΩ
RECAL_ENSometimes UsedSometimes UsedInternally pulled to VCC with 200 kΩ. When RECAL function is not used, GND with 1kΩ.
RFoutAP, RFoutAM, RFoutBP, RFoutBMSometimes UsedSometimes UsedIf both of the differential output pins are unused, the pins can be left floating and power down using SPI-mode or Mute the pins using Pin-mode options. If only one side of complimentary output is used, connect the unused pin to GND with 50 Ω through AC coupling capacitor.
OUTMUX2, OUTMUX1, OUTMUX0 Sometimes Used Always used GND with 1 kΩ
REF_DBLR_EN Never used Some times used GND with 1 kΩ
MuteA, MuteB Sometimes used Always used GND with 1 kΩ