SNAS849 December   2024 LMX2624-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

7.1 Device Registers

Table 7-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-1 must be considered as reserved locations and the register contents must not be modified.

Table 7-1 DEVICE Registers
Offset Acronym Register Name Section
0h R0 Section 7.1.1
1h R1 Section 7.1.2
2h R2 Section 7.1.3
3h R3 Section 7.1.4
4h R4 Section 7.1.5
5h R5 Section 7.1.6
6h R6 Section 7.1.7
7h R7 Section 7.1.8
8h R8 Section 7.1.9
9h R9 Section 7.1.10
Ah R10 Section 7.1.11
Bh R11 Section 7.1.12
Ch R12 Section 7.1.13
Dh R13 Section 7.1.14
Eh R14 Section 7.1.15
Fh R15 Section 7.1.16
10h R16 Section 7.1.17
11h R17 Section 7.1.18
12h R18 Section 7.1.19
13h R19 Section 7.1.20
14h R20 Section 7.1.21
16h R22 Section 7.1.22
17h R23 Section 7.1.23
1Eh R30 Section 7.1.24
1Fh R31 Section 7.1.25
20h R32 Section 7.1.26
22h R34 Section 7.1.27
23h R35 Section 7.1.28
4Fh R79 Section 7.1.29

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 Device Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.1.1 R0 Register (Offset = 0h) [Reset = B3CCh]

R0 is shown in Table 7-3.

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Table 7-3 R0 Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R/W 0h No description
14 VCO_PHASE_SYNC_EN R/W 0h Phase sync enable. Rising edge on Phase Sync pin triggers Phase Sync
13 DBLR_ACAL_EN R/W 1h Enables Doubler Amplitude calibration
0h = Double
12 DBLR_FCAL_EN R/W 1h Enables Doubler Frequency calibration
0h = Double calibration is disabled
1h = Enables doubler calibration (reg0 write)
11 ADR_HOLD R/W 0h Holds the address for SPI block Read/Write.
0h = Address is determined by ascend
1h = Address is determined by hold (Has priority over ascend)
10 ASCEND R/W 0h Direction of register update for SPI block write
0h = Address Descending
1h = Address Ascending
9-8 OPBUF_MUTE R/W 3h For unmuting channel A or B during calibration
0h = RFOUTB is not muted during FCAL
1h = RFOUTB is muted during FCAL
7-6 FCAL_SHIFT_LEFT R/W 3h Reduce the Nb4R, Rb4N (calibration)frequency by 2FCAL_SHIFT_LEFT.
Can be set according to PFD frequency (Fpd)
0h = Fpd ≤ 100MHz
1h = 100MHz < Fpd ≤ 150MHz
2h = 150MHz < Fpd ≤ 200MHz
3h = Fpd > 200MHz
5-4 FCAL_SHIFT_RIGHT R/W 0h Increase the Nb4R, Rb4N (calibration) frequency by 2FCAL_SHIFT_RIGHT during frequency calibration.
[Valid if PostR : k*2FCAL_SHIFT_RIGHT]
Can be set according to PFD frequency (Fpd)
0h = Fpd ≥ 10MHz
1h = 5MHz ≥Fpd< 10MHz
2h = 2.5MHz ≥Fpd< 5MHz
3h = Fpd< 2.5MHz
3 ACAL_EN R/W 1h Enables Amplitude calibration. This takes place only during frequency calibration
0h = No amplitude calibration
1h = Amplitude calibration along with frequency calibration
2 FCAL_EN R/W 1h Writing reg0 with this bit enabled as 1 triggers VCO frequency calibration
0h = Reg0 write does not trigger calibration
1h = Reg0 write triggers frequency calibration
1 RESET R/W 0h Reset all registers to default value
0h = Normal operation
1h = Writing 1, triggers reset. This register self returns to 0, but in TICSPro you have to write a 0 to return the register to default
0 POWERDOWN R/W 0h Power down the device
0h = Normal Operation
1h = Device power down

7.1.2 R1 Register (Offset = 1h) [Reset = 10CBh]

R1 is shown in Table 7-4.

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Table 7-4 R1 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14 PH_SYNC_EN R/W 0h Enable signal for fine tuning output delay through MASh seed
0h = Disable
1h = Enable
13 GLOBAL_READBACK R/W 0h Register readback control
0h = reads the written register values
1h = reads the state machine value of AS registers
12 LD_LOCK_EN R/W 1h Lock Detect Type.
VCOCal lock detect asserts a high output after the VCO has finished calibration and the LD_DLY timeout counter is finished.
Vtune and VCOCal lock detect asserts a high output when VCOCal lock detect asserts a signal and the tuning voltage to the VCO is within acceptable limits (continuous monitoring of Vtune voltage).
0h = VCOCal Lock Detect
1h = VCOCal and Vtune Lock Detect
11 MUTEB_POLARITY R/W 0h Selects if MUTEB pin is active high or active low.
0h = Mutes when pin is high
1h = Mutes when pin is low
10 MUTEA_POLARITY R/W 0h Selects if MUTEA pin is active high or active low.
MUTEA polarity
0h = Mutes when pin is high
1h = Mutes when pin is low
9 MUTEB_SEL R/W 0h Select if Path B is to be muted through pin or register.
0h = pin
1h = register
8 MUTEA_SEL R/W 0h Select if Path A is to be muted through pin or register.
0h = pin
1h = register
7 OUTBUFFB_MUTE R/W 1h Mutes path B
0h = RFOUTB is not muted
1h = RFOUTB is muted
6 OUTBUFFA_MUTE R/W 1h Mutes path A
0h = RFOUTA is not muted
1h = RFOUTA is muted
5 OUTBUFFB_PD R/W 0h Powering down Path B output buffer
0h = OUTBUFFB is powered on
1h = OUTBUFFB is powered off
4 OUTBUFFA_PD R/W 0h Powering down Path A output buffer
0h = OUTBUFFA is powered on
1h = OUTBUFFA is powered off
3 DBLR_PD R/W 1h Powering down doubler
0h = Doubler is powered on
1h = Doubler is powered off
2-0 SMCLK_DIV R/W 3h Digital clock is derived from OSC_IN clock which can go up to 800MHz. This register is used to restrict the clock input to digital to maximum accept able frequency of
SM_CLK = 50MHz
SM_CLK = OSCIN clock/(2^<SM_CLK_DIV>)
0h = /1 (for OSCIN ≤ 50MHz)
1h = /2 (for OSCIN ≤ 100MHz) /2
2h = /4 (for OSCIN ≤ 200MHz)
3h = /8 (for OSCIN ≤ 400MHz)
4h = /16 (for OSCIN ≤ 800MHz)
5h = /32 (OSCIN ≥ 800MHz)

7.1.3 R2 Register (Offset = 2h) [Reset = 0F3Fh]

R2 is shown in Table 7-5.

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Table 7-5 R2 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R/W 1h Program this field to 0x1.
10-6 CP2P5V_IUP R/W 1Ch Charge pump gain (UP)
0h = Unused
1h = Unused
2h = 3mA
3h = 3mA
4h = 1.5mA
5-3 OUTBUFFB_DACCTRL R/W 7h Control current (daccode) in final stage of OUTBUFFB
0h = 2.5mA
1h = 5mA
2h = 7.5mA
3h = 10mA
4h = 12.5mA
5h = 15mA
6h = 17.5mA
7h = 20mA
2-0 OUTBUFFA_DACCTRL R/W 7h Control current (daccode) in final stage of OUTBUFFA
0h = 2.5mA
1h = 5mA
2h = 7.5mA
3h = 10mA
4h = 12.5mA
5h = 15mA
6h = 17.5mA
7h = 20mA

7.1.4 R3 Register (Offset = 3h) [Reset = 5040h]

R3 is shown in Table 7-6.

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Table 7-6 R3 Register Field Descriptions
Bit Field Type Reset Description
15-14 OUTBUFFB_MUXSEL R/W 1h Selects OUTBUFFB configuration
0h = CHDIV
1h = VCO
2h = Invalid
3h = SYSREF
13-12 OUTBUFFA_MUXSEL R/W 1h Selects OUTBUFFA configuration
0h = CHDIV
1h = VCO
2h = DBLR
3h = Invalid
11 OUTMUX_PIN_CTRL R/W 0h Decides whether OUTMUX selection needs to be controlled through OUTMUX pins or OUTBUFFA/B_MUXSEL
0h = Controlled through pin
1h = Controlled through register
10-5 PFD_DLY R/W 2h Programmable phase detector delay. This must be programmed
based on VCO frequency, fractional order, and N divider value
DLY = (PFD_DLY_SEL + 3)*4*VCO_cycle
0h = Don't use PFD_DLY_SEL
1h = 16 VCO cycles
2h = 20 VCO cycles
3h = 24 VCO cycles
4h = ...
3Fh = 264 VCO cycles
4-0 CHDIV R/W 0h Channel divider (Equivalent Division) controls divider value of each segment of the channel divider
0h = NA
1h = /2
2h = /4
3h = /6
4h = /8
5h = /12
6h = /8
7h = /24
8h = /32
9h = /48
Ah = /64
Bh = /96
Ch = /128
Dh = /192
Eh = /256
Fh = /384
10h = /512
11h = /768
12h = /1024
13h = /1536

7.1.5 R4 Register (Offset = 4h) [Reset = 0710h]

R4 is shown in Table 7-7.

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Table 7-7 R4 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14 VCO_CAPCTRL_FORCE R/W 0h Allows forcing the VCO capcode value by manually programming the VCO_CAPCTRL register
13 VCO_IDAC_FORCE R/W 0h Allows forcing the VCODACISET to the value programmed in VCODACISET register
12 VCO_SEL_FORCE R/W 0h Allows forcing the VCO_SEL value to manually select the VCO
11 QUICK_STRT_EN R/W 0h Calibration starts with previous capcode (VCO_CAPCTRL), VCO (VCO_SEL) and idac code (VCODACISET) for quick calibration
10 FAST_ACAL_EN R/W 1h Fast acal enable
0h = FAST ACAL is disabled.
1h = FAST ACAL is enabled
9 FAST_FCAL_EN R/W 1h Fast fcal enable
0h = FAST FCAL is disabled.
1h = FAST FCAL is enabled
8-0 UNDISCLOSED R/W 110h Program this field to 0x110.

7.1.6 R5 Register (Offset = 5h) [Reset = 0F2Ch]

R5 is shown in Table 7-8.

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Table 7-8 R5 Register Field Descriptions
Bit Field Type Reset Description
15-13 MASH_ORDER R/W 0h Decides MASH order.
MASH order has limitation based on 'N' value used and frequency.
0h = Mash Disable
1h = 1st order
2h = 2nd order
3h = 3rd order
4h = 4th order
6Fh = > Invalid
12 FULL_ASSIST R/W 0h Force VCO and Dblr settings in Full Assist mode to avoid calibration.
VCO and Doubler takes user programmed value s for following registers - VCO_SEL, VCO_CAPCODE, VCODACISET, DBLR1_PD, DBLR_AMP_CAPCTRL, DBLR_AMP_DACCTRL, DBLR_PREGEN_AMP_CAPCTRL, DBLR_PREGEN_AMP_DACCTRL
11-9 VCO_SEL R/W 7h User specified start VCO.
If no value is written, calibration starts with VCO7 (default value) else calibration always starts with VCO7
0h = > Invalid
1h = VCO1
2h = VCO2
3h = VCO3
7h = VCO7
8-0 VCO_IDAC R/W 12Ch Idac bit setting for VCO. Adds extra 4uA bias current

7.1.7 R6 Register (Offset = 6h) [Reset = 41BFh]

R6 is shown in Table 7-9.

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Table 7-9 R6 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14-13 DBLR_AMP1_DACCTRL R/W 2h Control daccode in Doubler Amplifiers. Code the but according to the readback after dblr calibration.
12-9 DBLR_AMP_CAPCTRL R/W 0h Control capcode in Doubler Amplifiers. Code the bit according to the readback after dblr calibration.
8 DBLR1_PD R/W 1h To disable path1 for doubler. Needs override.
0h = Doubler1 path is powered on
1h = Doubler1 path is powered off
7-0 VCO_CAPCTRL R/W BFh cap code for VCO0-7. Usable range is from 191 to 0.

7.1.8 R7 Register (Offset = 7h) [Reset = 7D40h]

R7 is shown in Table 7-10.

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Table 7-10 R7 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14-7 FASTCHG_CYCLES R/W FAh Control number of SM cycles for which the fast charge is ON once reg0 is written in full_assist or double buffering mode. Recommended time = 5us
1h = 1SM clock cycle
2h = 2SM cycle
FFh = 255 SM clock cycles
6-4 DBLR_PREGEN_AMP_DACCTRL R/W 4h Control daccode in Doubler PreDriver Amplifier. Code the bit according to the readback after dblr calibration.
3-0 DBLR_PREGEN_AMP_CAPCTRL R/W 0h Control capcode in Doubler PreDriver Amplifier. Code the bit according to the readback after dblr calibration.

7.1.9 R8 Register (Offset = 8h) [Reset = 0046h]

R8 is shown in Table 7-11.

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Table 7-11 R8 Register Field Descriptions
Bit Field Type Reset Description
15-0 PLL_N[15:0] R/W 46h Integer part of NDIV (LSB)

7.1.10 R9 Register (Offset = 9h) [Reset = 0000h]

R9 is shown in Table 7-12.

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Table 7-12 R9 Register Field Descriptions
Bit Field Type Reset Description
15-13 PLL_N[18:16] R/W 0h Upper 3 bits of N mash, total 19 bits, split as 16 + 3
12-0 RESERVED R/W 0h No description

7.1.11 R10 Register (Offset = Ah) [Reset = DA80h]

R10 is shown in Table 7-13.

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Table 7-13 R10 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_DEN[15:0] R/W DA80h Denom of MASH Fraction (LSB)

7.1.12 R11 Register (Offset = Bh) [Reset = FD51h]

R11 is shown in Table 7-14.

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Table 7-14 R11 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_DEN[31:16] R/W FD51h Denom of MASH Fraction (MSB)

7.1.13 R12 Register (Offset = Ch) [Reset = 0000h]

R12 is shown in Table 7-15.

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Table 7-15 R12 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_SEED[15:0] R/W 0h Mash seed (LSB) Sets the initial state of the fractional engine. Useful for producing a phase shift and fractional spur optimization.

7.1.14 R13 Register (Offset = Dh) [Reset = 0000h]

R13 is shown in Table 7-16.

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Table 7-16 R13 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_SEED[31:16] R/W 0h Mash seed (MSB)

7.1.15 R14 Register (Offset = Eh) [Reset = 0000h]

R14 is shown in Table 7-17.

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Table 7-17 R14 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_NUM[15:0] R/W 0h Numerator of MASH fraction (LSB)

7.1.16 R15 Register (Offset = Fh) [Reset = 0000h]

R15 is shown in Table 7-18.

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Table 7-18 R15 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_NUM[31:16] R/W 0h Numerator of MASH fraction (MSB)

7.1.17 R16 Register (Offset = 10h) [Reset = 0001h]

R16 is shown in Table 7-19.

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Table 7-19 R16 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R 0h Program this field to 0x0.
8 DBL_BUF_EN R/W 0h Double buffering allows the user to program multiple registers without having them actually take effect till R0 is written
0h = Disables double buffering
1h = Enables doubler buffering
7-0 RDIV_POST R/W 1h Post R-divider value
1h = /1
2h = /2
FFh = /255

7.1.18 R17 Register (Offset = 11h) [Reset = 1001h]

R17 is shown in Table 7-20.

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Table 7-20 R17 Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h No description
12 REF_Doubler_EN R/W 1h Register control for doubler in reference path.
0h = Disable REF path doubler
1h = Enable Doubler
11-0 RDIV_PRE R/W 1h Pre R-divider valuec(First 8 bits)
All other bits are reserved.
1h = /1
2h = /2
80h = /128

7.1.19 R18 Register (Offset = 12h) [Reset = 0030h]

R18 is shown in Table 7-21.

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Table 7-21 R18 Register Field Descriptions
Bit Field Type Reset Description
15-5 SYSREF_DIV R/W 1h Fout = Fin/(2*SYSREF_DIV + 4)
0h = /4
1h = /6
2h = /8
3h = /10
7FFh = /4098
4-2 SYSREF_PRE_DIV R/W 4h SYSREF Input clock divider MUX
0h = div by 1
1h = div by 2
2h = div by 4
1 SYSREF_EN R/W 0h This is a master signal to enable entire sys ref module including repeater mode
0h = Disable SYSREF module
1h = Enable SYSREF module
0 SYSREF_MODE R/W 0h Set the device in master or repeater mode.
0h = Master mode (Internally generated sysref)
1h = Engages repeater mode (Enabled typically when a sysref signal is generated by an external device and needs to be "passed" by the device).

7.1.20 R19 Register (Offset = 13h) [Reset = 01F8h]

R19 is shown in Table 7-22.

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Table 7-22 R19 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14-9 JESD_DAC2 R/W 0h Programmable delay for SYSREF output
8-3 JESD_DAC1 R/W 3Fh The register bits represent DAC stages to be enabled, each reg set representing 63 stages and each code corresponds to a delay step in final output.
2 SYSREF_RPTR_NONSYNCMODE_EN R/W 0h Enables sysref in repeater non-sync mode
0h = Device is in sync mode
1h = Device is in Non-sync mode if repeater mode is selected.
1 UNDISCLOSED R/W 0h Program this field to 0x0.
0 SYSREF_PULSE_EN R/W 0h Sets the device for continuous sysref pulses or fixed number of pulses. The number of pulses is programmed through SYSREF_RPT_CNT register.
0h = Continuous mode
1h = Pulsed mode

7.1.21 R20 Register (Offset = 14h) [Reset = 0000h]

R20 is shown in Table 7-23.

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Table 7-23 R20 Register Field Descriptions
Bit Field Type Reset Description
15-12 SYSREF_PULSE_CNT R/W 0h Used in N-shot mode to determine number of cycles SYSREF output is present. Setting this to zero is an allowable, but not practical state.
1h = 1pulses
2h = 2pulses
Fh = 15 pulses
11-6 JESD_DAC4 R/W 0h Programmable delay for SYSREF output
5-0 JESD_DAC3 R/W 0h Programmable delay for SYSREF output

7.1.22 R22 Register (Offset = 16h) [Reset = 0001h]

R22 is shown in Table 7-24.

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Table 7-24 R22 Register Field Descriptions
Bit Field Type Reset Description
15-8 UNDISCLOSED R 0h Program this field to 0x0.
7 UNDISCLOSED R/W 0h Program this field to 0x0.
6-0 MUXOUT_TM_SEL R/W 1h User Debug
0h = lock_detect
1h = lock_detect
2h = Refout Clock(divided)
3h = SM Clock

7.1.23 R23 Register (Offset = 17h) [Reset = 09C4h]

R23 is shown in Table 7-25.

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Table 7-25 R23 Register Field Descriptions
Bit Field Type Reset Description
15-0 LD_DLY R/W 9C4h For the VCOCal lock detect, this is the SM cycles that is added after the calibration is finished before the VCOCal lock detect is asserted high.

7.1.24 R30 Register (Offset = 1Eh) [Reset = D6D8h]

R30 is shown in Table 7-26.

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Table 7-26 R30 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_RST_COUNT[15:0] R/W D6D8h Mash counter for applying reset puls (lower 16 bits)

7.1.25 R31 Register (Offset = 1Fh) [Reset = 0000h]

R31 is shown in Table 7-27.

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Table 7-27 R31 Register Field Descriptions
Bit Field Type Reset Description
15-0 MASH_RST_COUNT[31:16] R/W 0h Mash counter for applying reset pulse (upper 16 bits)- 16 bit unsigned integer
This delay is used to verify that the reliable reset is provided to the mash circuit only after device is locked when using phase SYNC. This in turn verifies that during multi device sync scenario same Mash output sequence is maintained. The delay must be set at least four times the PLL lock time. This delay is expressed in state machine clock periods.
One of these periods is equal to 2SM_CLK_DIV/Fosc

7.1.26 R32 Register (Offset = 20h) [Reset = 026Fh]

R32 is shown in Table 7-28.

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Table 7-28 R32 Register Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h No description
9-3 WD_DLY R/W 4Dh Delay for the internal watchdog timer. The timer is internally multiplied by 214. Default value is 25ms with 50MHz SM CLK.
2-0 WD_CNTRL R/W 7h Watchdog Control
0h = Digital Watchdog disabled.
1h = Watchdog triggers 1 time
2h = Watchdog triggers up to 2 times
3h = Watchdog triggers up to 3 times
4h = Watchdog triggers up to 4 times
5h = Watchdog triggers up to 5 times
6h = Watchdog triggers up to 6 times
7h = Watchdog retriggers as many times as necessary with no limit.

7.1.27 R34 Register (Offset = 22h) [Reset = 00F1h]

R34 is shown in Table 7-29.

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Table 7-29 R34 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_VER_ID R F1h Readback: version ID

7.1.28 R35 Register (Offset = 23h) [Reset = 0000h]

R35 is shown in Table 7-30.

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Table 7-30 R35 Register Field Descriptions
Bit Field Type Reset Description
15-6 RESERVED R/W 0h No description
5 rb_LD_VTUNELO_CMPO R 0h Readback: lock detect low comparator output
4 rb_LD_VTUNEHI_CMPO R 0h Readback: lock detect hi comparator output
3-1 rb_VCO_SELECT_RB R 0h Readback: indicates current VCO selected
0 rb_VCO_CT_CAL_RUNNING R 0h Readback: high if FCAL is running

7.1.29 R79 Register (Offset = 4Fh) [Reset = 0003h]

R79 is shown in Table 7-31.

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Table 7-31 R79 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14-0 UNDISCLOSED R/W 3h Program this field to 0x3.