SNAS849 Data sheet

SNAS849A December 2024 – July 2026 LMX2624-SP

PRODUCTION DATA

6.5.3.1 Device Registers

Table 6-24 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 6-24 should be considered as reserved locations and the register contents should not be modified.

Table 6-24 DEVICE Registers

Offset	Acronym	Section
0h	R0	Section 5.3.1.1
1h	R1	Section 5.3.1.2
2h	R2	Section 5.3.1.3
3h	R3	Section 5.3.1.4
4h	R4	Section 5.3.1.5
5h	R5	Section 5.3.1.6
6h	R6	Section 5.3.1.7
7h	R7	Section 5.3.1.8
8h	R8	Section 5.3.1.9
9h	R9	Section 5.3.1.10
Ah	R10	Section 5.3.1.11
Bh	R11	Section 5.3.1.12
Ch	R12	Section 5.3.1.13
Dh	R13	Section 5.3.1.14
Eh	R14	Section 5.3.1.15
Fh	R15	Section 5.3.1.16
10h	R16	Section 5.3.1.17
11h	R17	Section 5.3.1.18
12h	R18	Section 5.3.1.19
13h	R19	Section 5.3.1.20
14h	R20	Section 5.3.1.21
16h	R22	Section 5.3.1.22
17h	R23	Section 5.3.1.23
1Eh	R30	Section 5.3.1.24
1Fh	R31	Section 5.3.1.25
20h	R32	Section 5.3.1.26
22h	R34	Section 5.3.1.27
23h	R35	Section 5.3.1.28
54h	R84	Section 5.3.1.29

Complex bit access types are encoded to fit into small table cells. Table 6-25 shows the codes that are used for access types in this section.

Table 6-25 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

5.3.1.1 R0 Register (Offset = 0h) [Reset = 33CCh]

R0 is shown in Table 6-26.

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Table 6-26 R0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14	VCO_PHASE_SYNC	R/W	0h	Phase sync enable. If this bit is set as 1, a rising edge on SYNC pin triggers phase synchronization. SYSREF operation requires this bit set to 1. 0h = No phase synchronization 1h = Phase synchronization enabled
13	UNDISCLOSED	R/W	1h	Program this field to 0x1.
12	FCAL_DBLR_EN	R/W	1h	Enable bit for VCO doubler calibration. If this bit is set as 1, VCO doubler will be calibrated whenever VCO calibration is triggered. 0h = No VCO doubler calibration 1h = VCO doubler calibration enabled
11-10	UNDISCLOSED	R/W	0h	Program this field to 0x0.
9-8	OUT_MUTE	R/W	3h	Defines how to mute RF output during VCO calibration. If mute is selected, at least one VCO calibration has to be executed otherwise the selected mute channel will be muted. 0h = RFOUTA, RFOUTB not muted 1h = RFOUTA muted; RFOUTB not muted 2h = RFOUTA not muted; RFOUTB muted 3h = RFOUTA, RFOUTB muted
7-6	FCAL_HPFD_ADJ	R/W	3h	Adjustment to decrease the f_PD frequency for use in VCO calibration. Set this field in accordance to the phase detector frequency for optimal VCO calibration. 0h = f_PD ≤ 50MHz 1h = 50MHz < f_PD ≤ 100MHz 2h = 100MHz < f_PD ≤ 200MHz 3h = f_PD > 200MHz
5-4	FCAL_LPFD_ADJ	R/W	0h	Adjustment to increase the f_PD frequency for use in VCO calibration. Set this field in accordance to the phase detector frequency for optimal VCO calibration. 0h = f_PD ≥ 10MHz 1h = 5MHz ≤ f_PD < 10MHz 2h = 2.5MHz ≤ f_PD < 5MHz 3h = f_PD < 2.5MHz
3	UNDISCLOSED	R/W	1h	Program this field to 0x1.
2	FCAL_EN	R/W	1h	Writing register R0 with this bit enabled as 1 triggers VCO calibration. 0h = No calibration 1h = Writing 1 triggers VCO calibration
1	RESET	R/W	0h	Resets all registers to silicon default values. Re-programming of all registers is required after a reset. 0h = Normal operation 1h = Writing 1 triggers reset
0	POWERDOWN	R/W	0h	Powers down the device. Register contents are retained when the device is powered down. 0h = Normal Operation 1h = Device power down

5.3.1.2 R1 Register (Offset = 1h) [Reset = 10CBh]

R1 is shown in Table 6-27.

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Table 6-27 R1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14	MASH_SEED_EN	R/W	0h	Enables MASH_SEED for phase adjustment. 0h = Disabled 1h = Enabled
13	READBACK	R/W	0h	Sets register read back control. 0h = Reads the written register values 1h = Reads the state machine values
12	LD_TYPE	R/W	1h	Defines Lock Detect type. VCOCal Lock Detect asserts a high output after the VCO has finished calibration and the LD_DLY timeout counter is finished. Vtune and VCOCal Lock Detect asserts a high output when VCOCal Lock Detect would assert a signal and the tuning voltage to the VCO is within acceptable limits (continuous monitoring of Vtune voltage). RECAL feature requires using Vtune and VCOCal Lock Detect. Both Lock Detect types require VCO calibration is executed at least one time, otherwise the output will stay low. 0h = VCOCal Lock Detect 1h = Vtune and VCOCal Lock Detect
11	OUTB_MUTE_POL	R/W	0h	Selects if MUTEB pin is active high or active low. 0h = Mutes when pin is high 1h = Mutes when pin is low
10	OUTA_MUTE_POL	R/W	0h	Selects if MUTEA pin is active high or active low. 0h = Mutes when pin is high 1h = Mutes when pin is low
9	OUTB_MUTE_PIN	R/W	0h	Selects if RFOUTB is muted through pin or register. 0h = Muted by pin 1h = Muted by register
8	OUTA_MUTE_PIN	R/W	0h	Selects if RFOUTA is muted through pin or register. 0h = Muted by pin 1h = Muted by register
7	OUTB_MUTE	R/W	1h	Mutes RFOUTB. 0h = RFOUTB is not muted 1h = RFOUTB is muted
6	OUTA_MUTE	R/W	1h	Mutes RFOUTA. 0h = RFOUTA is not muted 1h = RFOUTA is muted
5	OUTB_PD	R/W	0h	Powers down RFOUTB. 0h = RFOUTB is powered on 1h = RFOUTB is powered off
4	OUTA_PD	R/W	0h	Powers down RFOUTA. 0h = RFOUTA is powered on 1h = RFOUTA is powered off
3	UNDISCLOSED	R/W	1h	Program this field to 0x1.
2-0	CAL_CLK_DIV	R/W	3h	Sets state machine clock frequency equal to or less than 50MHz. f_SM = f_OSC / 2^CAL_CLK_DIV 0h = f_OSC ≤ 50MHz 1h = f_OSC ≤ 100MHz 2h = f_OSC ≤ 200MHz 3h = f_OSC ≤ 400MHz 4h = f_OSC ≤ 800MHz 5h = f_OSC > 800MHz

5.3.1.3 R2 Register (Offset = 2h) [Reset = 0F3Fh]

R2 is shown in Table 6-28.

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Table 6-28 R2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	UNDISCLOSED	R/W	1h	Program this field to 0x1.
10-8	CPG	R/W	7h	Sets charge pump current. 0h = Tri-state 1h = 6 mA 2h = Reserved 3h = 12 mA 4h = 3 mA 5h = 9 mA 6h = Reserved 7h = 15 mA
7-6	UNDISCLOSED	R/W	0h	Program this field to 0x0.
5-3	OUTB_PWR	R/W	7h	Controls RFOUTB output power. Higher values give more output power.
2-0	OUTA_PWR	R/W	7h	Controls RFOUTA output power. Higher values give more output power.

5.3.1.4 R3 Register (Offset = 3h) [Reset = 5040h]

R3 is shown in Table 6-29.

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Table 6-29 R3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	OUTB_MUX	R/W	1h	Selects RFOUTB configuration. 0h = Divided down output 1h = Direct VCO output 2h = VCO doubler output 3h = SYSREF output
13-12	OUTA_MUX	R/W	1h	Selects RFOUTA configuration. 0h = Divided down output 1h = Direct VCO output 2h = VCO doubler output 3h = Reserved
11	OUTMUX	R/W	0h	Decides whether RF output selection ( divided down, direct VCO or VCO doubler output) is controlled through OUTMUX pins or register. 0h = Controlled through pin 1h = Controlled through register
10-5	PFD_DLY	R/W	2h	Programmable phase detector delay. This should be programmed based on VCO frequency, fractional order, and N divider value. All other values must be set in accordance to the N divider value 0h = Reserved
4-0	CHDIV	R/W	0h	Sets VCO frequency divider value for RF output. Values not listed in the following are reserved. 1h = Divide by 2 2h = Divide by 4 3h = Divide by 6 4h = Divide by 8 5h = Divide by 12 6h = Divide by 16 7h = Divide by 24 8h = Divide by 32 9h = Divide by 48 Ah = Divide by 64 Bh = Divide by 96 Ch = Divide by 128 Dh = Divide by 192 Eh = Divide by 256 Fh = Divide by 384 10h = Divide by 512 11h = Divide by 768 12h = Divide by 1024 13h = Divide by 1536

5.3.1.5 R4 Register (Offset = 4h) [Reset = 0644h]

R4 is shown in Table 6-30.

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Table 6-30 R4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14	VCO_CAPCTRL_FORCE	R/W	0h	Allows forcing the device to use the programmed VCO_CAPCTRL value for the VCO. 0h = Disabled 1h = Enabled
13	VCO_DACISET_FORCE	R/W	0h	Allows forcing the device to use the programmed VCO_DACISET value for the VCO. 0h = Disabled 1h = Enabled
12	VCO_SEL_FORCE	R/W	0h	Allows forcing the device to use the programmed VCO_SEL value to manually select the VCO core. 0h = Disabled 1h = Enabled
11	QUICK_RECAL_EN	R/W	0h	Selects VCO configuration (VCO_CAPCTRL, VCO_SEL and VCO_DACISET) values for VCO calibration to begin with. 0h = Use programmed VCO configuration 1h = Use current VCO configuration state machine values
10-0	UNDISCLOSED	R/W	644h	Program this field to 0x644.

5.3.1.6 R5 Register (Offset = 5h) [Reset = 0F2Ch]

R5 is shown in Table 6-31.

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Table 6-31 R5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	MASH_ORDER	R/W	0h	Sets the MASH order. When MASH is disabled, the fractional numerator (PLL_NUM) is ignored. Values not listed in the following are reserved. 0h = MASH disabled 1h = First order modulator 2h = Second order modulator 3h = Third order modulator
12	VCO_FULL_ASSIST	R/W	0h	Enabling this bit forces the device to use the programmed value for the following fields: VCO_SEL, VCO_CAPCTRL, VCO_DACISET DBLR1_PD, DBLR_AMP_CAPCTRL, DBLR_AMP1_DACCTRL DBLR_PG_AMP_CAPCTRL, DBLR_PG_AMP_DACCTRL If enabled, DBL_BUF_EN = 1 is required. 0h = Disabled 1h = Enabled
11-9	VCO_SEL	R/W	7h	Sets the initial VCO core for VCO calibration. Unless QUICK_RECAL_EN = 1, VCO calibration always start with the value specified in this field. 0h = Reserved 1h = VCO1 2h = VCO2 3h = VCO3 4h = VCO4 5h = VCO5 6h = VCO6 7h = VCO7
8-0	VCO_DACISET	R/W	12Ch	Sets the initial value for VCO calibration, typical value is 300. Unless QUICK_RECAL_EN = 1, VCO calibration always start with the value specified in this field.

5.3.1.7 R6 Register (Offset = 6h) [Reset = 41BFh]

R6 is shown in Table 6-32.

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Table 6-32 R6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14-13	DBLR_AMP1_DACCTRL	R/W	2h	VCO doubler configuration. Programming is required only with full assist mode. Field value is obtained by reading back the register after VCO doubler calibration.
12-9	DBLR_AMP_CAPCTRL	R/W	0h	VCO doubler configuration. Programming is required only with full assist mode. Field value is obtained by reading back the register after VCO doubler calibration.
8	DBLR1_PD	R/W	1h	Disables path 1 for VCO doubler. Programming is required only with full assist mode. Field value is obtained by reading back the register after VCO doubler calibration. 0h = Doubler path 1 is enabled 1h = Doubler path 1 is disabled
7-0	VCO_CAPCTRL	R/W	BFh	Sets the initial value for VCO calibration. Valid values are between 0 and 191. Higher value represents lower VCO frequency. Unless QUICK_RECAL_EN = 1, VCO calibration always start with the value specified in this field.

5.3.1.8 R7 Register (Offset = 7h) [Reset = 7D40h]

R7 is shown in Table 6-33.

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Table 6-33 R7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14-7	VCO_FASTCHG_CNT	R/W	FAh	Sets the fast charge ON time for use in full assist mode or when double buffering is enabled. ON time = VCO_FASTCHG_CNT / f_SM Recommended ON time is 5µs.
6-4	DBLR_PG_AMP_DACCTRL	R/W	4h	VCO doubler configuration. Programming is required only with full assist mode. Field value is obtained by reading back the register after VCO doubler calibration.
3-0	DBLR_PG_AMP_CAPCTRL	R/W	0h	VCO doubler configuration. Programming is required only with full assist mode. Field value is obtained by reading back the register after VCO doubler calibration.

5.3.1.9 R8 Register (Offset = 8h) [Reset = 0046h]

R8 is shown in Table 6-34.

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Table 6-34 R8 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_N	R/W	46h	Lower 16 bits of N-divider, total 19 bits.

5.3.1.10 R9 Register (Offset = 9h) [Reset = 0000h]

R9 is shown in Table 6-35.

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Table 6-35 R9 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	PLL_N[18:16]	R/W	0h	Upper 3 bits of N-divider, total 19 bits.
12-0	UNDISCLOSED	R/W	0h	Program this field to 0x0.

5.3.1.11 R10 Register (Offset = Ah) [Reset = DA80h]

R10 is shown in Table 6-36.

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Table 6-36 R10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_DEN[15:0]	R/W	DA80h	Lower 16 bits of fractional denominator, total 32 bits.

5.3.1.12 R11 Register (Offset = Bh) [Reset = FD51h]

R11 is shown in Table 6-37.

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Table 6-37 R11 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_DEN[31:16]	R/W	FD51h	Upper 16 bits of fractional denominator, total 32 bits.

5.3.1.13 R12 Register (Offset = Ch) [Reset = 0000h]

R12 is shown in Table 6-38.

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Table 6-38 R12 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASH_SEED[15:0]	R/W	0h	Lower 16 bits of MASH_SEED, total 32 bits.

5.3.1.14 R13 Register (Offset = Dh) [Reset = 0000h]

R13 is shown in Table 6-39.

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Table 6-39 R13 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASH_SEED[31:16]	R/W	0h	Upper 16 bits of MASH_SEED, total 32 bits.

5.3.1.15 R14 Register (Offset = Eh) [Reset = 0000h]

R14 is shown in Table 6-40.

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Table 6-40 R14 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_NUM[15:0]	R/W	0h	Lower 16 bits of fractional numerator, total 32 bits.

5.3.1.16 R15 Register (Offset = Fh) [Reset = 0000h]

R15 is shown in Table 6-41.

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Table 6-41 R15 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_NUM[31:16]	R/W	0h	Upper 16 bits of fractional numerator, total 32 bits.

5.3.1.17 R16 Register (Offset = 10h) [Reset = 0001h]

R16 is shown in Table 6-42.

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Table 6-42 R16 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	UNDISCLOSED	R/W	0h	Program this field to 0x0.
8	DBL_BUF_EN	R/W	0h	Enables double buffering. Double buffering allows the user to program multiple registers without having them actually take effect until register R0 is written. When this bit is enabled, sufficient fast charge ON time needs to be set. Full Assist Mode requires this bit set to 1. 0h = Disables double buffering 1h = Enables double buffering
7-0	PLL_R	R/W	1h	Reference path Post-R divider. This is the divider after the Pre-R divider.

5.3.1.18 R17 Register (Offset = 11h) [Reset = 1001h]

R17 is shown in Table 6-43.

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Table 6-43 R17 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	UNDISCLOSED	R/W	0h	Program this field to 0x0.
12	OSC_2X	R/W	1h	Enables reference path input clock doubler. 0h = Disabled 1h = Enabled
11-0	PLL_R_PRE	R/W	1h	Reference path Pre-R divider. The upper 4 bits are not used.

5.3.1.19 R18 Register (Offset = 12h) [Reset = 0030h]

R18 is shown in Table 6-44.

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Table 6-44 R18 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	SYSREF_DIV	R/W	1h	This divider further divides the clock frequency for SYSREF output.
4-2	SYSREF_DIV_PRE	R/W	4h	This divider is used to reduce the clock frequency to the SYSREF divider. Output frequency of this divider should be between 800MHz and 1.5GHz. Values not listed in the following are reserved. 1h = Bypassed 2h = Divide by 2 4h = Divide by 4
1	SYSREF_EN	R/W	0h	Enables SYSREF mode. 0h = Disables SYSREF module 1h = Enables SYSREF module
0	SYSREF_REPEAT	R/W	0h	Sets the device in SYSREF generation or repeater mode. In generation mode, SYSREF clocks are generated with internal circuitry. In repeater mode, incoming SYSREF signal passes through the device without reclocking. 0h = Generation mode 1h = Repeater mode

5.3.1.20 R19 Register (Offset = 13h) [Reset = 01F8h]

R19 is shown in Table 6-45.

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Table 6-45 R19 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	UNDISCLOSED	R/W	0h	Program this field to 0x0.
14-9	JESD_DAC2	R/W	0h	Programmable delay for SYSREF output.
8-3	JESD_DAC1	R/W	3Fh	Programmable delay for SYSREF output.
2	RPTR_NONSYNC	R/W	0h	Enables non-synchronous SYSREF repeater mode. In SYSREF repeater mode, if this bit is set to 1, the output SYSREF clock will not be re-clocked with the VCO, allowing the input SYSREF clock to pass through the device directly. 0h = Reclocking with VCO 1h = Passing through without reclocking
1	UNDISCLOSED	R/W	0h	Program this field to 0x0.
0	SYSREF_PULSE	R/W	0h	Sets the device for continuous SYSREF pulses or fixed number of pulses. In continuous mode, SYSREF pulses are generated continuously. Pulsed mode allows multiple pulses, as determined by SYSREF_PULSE_CNT, to be sent out whenever the SysRefReq pin goes HIGH. 0h = Continuous mode 1h = Pulsed mode

5.3.1.21 R20 Register (Offset = 14h) [Reset = 0000h]

R20 is shown in Table 6-46.

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Table 6-46 R20 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	SYSREF_PULSE_CNT	R/W	0h	Defines how many pulses are sent in SYSREF pulsed mode. Valid values are between 1 and 15.
11-6	JESD_DAC4	R/W	0h	Programmable delay for SYSREF output.
5-0	JESD_DAC3	R/W	0h	Programmable delay for SYSREF output.

5.3.1.22 R22 Register (Offset = 16h) [Reset = 0001h]

R22 is shown in Table 6-47.

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Table 6-47 R22 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	UNDISCLOSED	R/W	0h	Program this field to 0x0.
6-0	MUXOUT	R/W	1h	Selects the functionality of the MUXOUT pin. 0h = Lock detect 1h = Register read back 2h = f_PD / 32 3h = f_SM / 32

5.3.1.23 R23 Register (Offset = 17h) [Reset = 09C4h]

R23 is shown in Table 6-48.

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Table 6-48 R23 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	LD_DLY	R/W	9C4h	For the VCOCal Lock Detect type, this is the delay in state machine clock cycles that is added after the calibration is finished before the lock detect is asserted high. Delay time = LD_DLY × 4 / f_SM

5.3.1.24 R30 Register (Offset = 1Eh) [Reset = D6D8h]

R30 is shown in Table 6-49.

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Table 6-49 R30 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASH_RST_COUNT[15:0]	R/W	D6D8h	Lower 16 bits of MASH_RST_COUNT, total 32 bits. This field defines the delay time that is necessary after the MASH engine is reset during phase synchronization. When PLL_NUM is not zero, the delay time should be set to at least four times the PLL lock time. This field can be set to 0 when PLL_NUM = 0. Delay time = MASH_RST_COUNT / f_SM

5.3.1.25 R31 Register (Offset = 1Fh) [Reset = 0000h]

R31 is shown in Table 6-50.

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Table 6-50 R31 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASH_RST_COUNT[31:16]	R/W	0h	Upper 16 bits of MASH_RST_COUNT, total 32 bits.

5.3.1.26 R32 Register (Offset = 20h) [Reset = 026Fh]

R32 is shown in Table 6-51.

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Table 6-51 R32 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	UNDISCLOSED	R/W	0h	Program this field to 0x0.
9-3	WD_DLY	R/W	4Dh	Delay for the internal watchdog timer. Delay time = WD_DLY × 2¹⁴ / f_SM
2-0	WD_CNTRL	R/W	7h	Watchdog control. 0h = Digital Watchdog disabled 1h = Watchdog triggers 1 time 2h = Watchdog triggers up to 2 times 3h = Watchdog triggers up to 3 times 4h = Watchdog triggers up to 4 times 5h = Watchdog triggers up to 5 times 6h = Watchdog triggers up to 6 times 7h = Watchdog retriggers as many times as necessary with no limit

5.3.1.27 R34 Register (Offset = 22h) [Reset = 0000h]

R34 is shown in Table 6-52.

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Table 6-52 R34 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rb_VER_ID	R	0h	Reads back device version ID.

5.3.1.28 R35 Register (Offset = 23h) [Reset = 0000h]

R35 is shown in Table 6-53.

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Table 6-53 R35 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	UNDISCLOSED	R/W	0h	Program this field to 0x0.
5-4	rb_LD_VTUNE	R	0h	Read back field for lock detect status. Applicable only when register R0 is programmed at least one time with LD_TYPE = 1, FCAL_EN bit is don't care. Values not listed in the following mean unlocked. 2h = Locked
3-1	rb_VCO_SEL	R	0h	Reads back the actual VCO core that the VCO calibration has selected. 0h = Reserved 1h = VCO1 2h = VCO2 3h = VCO3 4h = VCO4 5h = VCO5 6h = VCO6 7h = VCO7
0	UNDISCLOSED	R	0h	Program this field to 0x0.

5.3.1.29 R84 Register (Offset = 54h) [Reset = 0000h]

R84 is shown in Table 6-54.

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Table 6-54 R84 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	UNDISCLOSED	R/W	0h	Program this field to 0x4000. Note that this is different than the reset value.