SNAS849 December   2024 LMX2624-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

4 Pin Configuration and Functions

Figure 4-1 HBD Package64-Pin CQFPTop View
Table 4-1 Pin Functions
PINI/OTYPEDESCRIPTION
NO.NAME
1NDIV2I4-level pinInteger N divider bit 2 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
2NDIV1I4-level pinInteger N divider bit 1 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
3NDIV0I4-level pinInteger N divider bit 0 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
4 GND — — Ground
5 VbiasVCO — — VCO bias. Requires connecting 10-µF capacitor to ground. Place close to pin.
6 GND — — Ground
7 REF_DBLR_EN I — Input Reference Doubler enable in Pin-mode. A HIGH on this pin enables the reference doubler and LOW on this pin bypass the Input Reference Doubler. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
8 CAL/CE I — Chip enable. In Pin Mode (not SPI-mode), rising edges presented to this pin activate the VCO calibration. In SPI-mode, this pin acts like CE where a high on CE pin make device to enable and Low disables the device.
9SYNCI—Phase synchronization input pin.
10GND——Ground
11VccDIG——Digital supply. Recommend connecting 0.1-µF capacitor to ground.
12OSCinPI—Complimentary Reference input clock pins. High input impedance. Requires connecting series capacitor (0.1 µF recommended).
13OSCinMI—Complimentary pin to OSCinP.
14VregIN——Input reference path regulator decoupling. Requires connecting 1-µF capacitor to ground. Place close to pin.
15OUTMUX2I—Controls the Output Mux selection together with OUTMUX1 and OUTMUX0 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
16OUTMUX1I—Controls the Output Mux selection together with OUTMUX2 and OUTMUX0 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
17OUTMUX0I—Controls the Output Mux selection together with OUTMUX2 and OUTMUX1 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
18 MuteA I — Output Buffer mute control. High-impedance CMOS input. RFOUTA is muted or unmuted using this MuteA pin
19MuteBI—Output Buffer mute control. High-impedance CMOS input. RFOUTB is muted or unmuted using this MuteB pin
20VccCPI—Charge pump supply. Recommend connecting 0.1-µF capacitor to ground.
21CPoutO—Charge pump output. Recommend connecting C1 of loop filter close to charge pump pin.
22GND—GroundGround
23GND—GroundGround
24VccMASH——Digital supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
25SCKI—SPI input clock. High impedance CMOS input. 1.8 – 3.3V logic.
26SDII—SPI input data. High impedance CMOS input. 1.8 – 3.3V logic.
27VccBUF——Output buffer supply. Requires connecting 0.1-µF capacitor to ground.
28GND—GroundGround
29RFoutBMO—Complementary pin for RFoutBP
30RFoutBPO—Differential output B Pair. Requires connecting a 50-Ω resistor pullup to VCC as close as possible to pin. Can be used as a synthesizer output or SYSREF output.
31GND—GroundGround
32VccBUF——Output buffer supply. Requires connecting 0.1-µF capacitor to ground.
33NC——No connection. Leave Unconnected.
34MUXout——Multiplexed output pin. Can output: lock detect, SPI readback and diagnostics.
35CSB—SPI chip select bar. High impedance CMOS input. 1.8 – 3.3-V logic.
36GND—GroundGround
37VccBUF——Output buffer supply. Requires connecting 0.1-µF capacitor to ground.
38GND—GroundGround
39 RFoutAM O — Differential output A Pair. 50-Ω resistor pullup to VCC is integrated.
40 RFoutAP O — Differential output A Pair. 50-Ω resistor pullup to VCC is integrated.
41GND—GroundGround
42VccBUF——Output buffer supply. Requires connecting 0.1-µF capacitor to ground.
43GND—GroundGround
44VccVCO2——VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
45VbiasVCO2——VCO bias. Requires connecting 1-µF capacitor to ground.
46SysRefReqI—SYSREF request single ended input for JESD204B support.
47VrefVCO2——VCO supply reference. Requires connecting 10-µF capacitor to ground.
48RECAL_ENI—Enables the automatic recalibration feature. Low on this pin does not trigger calibration. High on this means the calibration is triggered whenever the device is unlocked after certain delay.
49 CDIV0 I 4-level pin Controls the Channel Divider along with CDIV2 and CDIV1 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
50 CDIV1 I 4-level pin Controls the Channel Divider along with CDIV0 and CDIV2 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
51 CDIV2 I 4-level pin Controls the Channel Divider along with CDIV1 and CDIV0 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
52GND—GroundGround
53VbiasVARAC——VCO Varactor bias. Requires connecting 10-µF capacitor to ground.
54GND—GroundGround
55VtuneI—VCO tuning voltage input.
56VrefVCO——VCO supply reference. Requires connecting 10-µF capacitor to ground.
57VccVCO——VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
58VregVCO——VCO regulator node. Requires connecting 1-µF capacitor to ground.
59GND—GroundGround
60GND—GroundGround
61NC—NCNo Connect
62NDIV5I4-level pinInteger N divider bit 5 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
63NDIV4I4-level pinInteger N divider bit 4 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
64NDIV3I4-level pinInteger N divider bit 3 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.