SNAS849A December   2024  – July 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples
    2. 10.2 Package Option Addendum
    3. 10.3 Tape and Reel Information

4 Pin Configuration and Functions

Figure 4-1 HBD Package 64-Pin CQFP Top View
Table 4-1 Pin Functions
PIN TYPE(1) TYPE DESCRIPTION
NO. NAME
1 NDIV2 I 4-level pin Integer N divider bit 2 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
2 NDIV1 I 4-level pin Integer N divider bit 1 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
3 NDIV0 I 4-level pin Integer N divider bit 0 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
4 GND — — Ground
5 VbiasVCO — — VCO bias. Requires connecting 10µF capacitor to ground. Place close to pin.
6 GND — — Ground
7 REF_DBLR_EN I — Input Reference Doubler enable in Pin-mode. A HIGH on this pin enables the reference doubler and LOW on this pin bypass the Input Reference Doubler. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
8 CAL/CE I — Chip enable. In Pin Mode (not SPI-mode), rising edges presented to this pin activate the VCO calibration. In SPI-mode, this pin acts like CE where a high on CE pin make device to enable and Low disables the device.
9 SYNC I — Phase synchronization SYNC signal input pin. CMOS input. If not being used, connect to ground using a 1kΩ resistor.
10 GND — — Ground
11 VccDIG — — Digital supply. Connect to 3.3V with a 0.1µF capacitor to ground.
12 OSCinP I — Reference Input clock pin (+). High input impedance. Requires connecting series capacitor (0.1µF recommended). For single-ended input, 50Ω resistor to GND needed before AC-coupling series capacitor. For Differential input, use 100Ω resistor between OSCinP and OSCinM.
13 OSCinM I — Complimentary pin to OSCinP (-). If not being used, AC-coupled to GND through a 50Ω resistor.
14 VregIN — — Input reference path regulator decoupling. Requires connecting 1µF capacitor to ground. Place close to pin.
15 OUTMUX2 I — Controls the Output Mux selection together with OUTMUX1 and OUTMUX0 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
16 OUTMUX1 I — Controls the Output Mux selection together with OUTMUX2 and OUTMUX0 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
17 OUTMUX0 I — Controls the Output Mux selection together with OUTMUX2 and OUTMUX1 for RFOUTA and RFOUTB. The eight options include selecting VCO output, Doubler output or Channel Divider output combinations for RFOUTA and RFOUTB. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
18 MuteA I — Output Buffer mute control. High-impedance CMOS input. RFOUTA is muted or unmuted using a MuteA pin
19 MuteB I — Output Buffer mute control. High-impedance CMOS input. RFOUTB is muted or unmuted using a MuteB pin
20 VccCP I — Charge pump supply. Connect to 3.3V with a 0.1µF capacitor to ground.
21 CPout O — Charge pump output. Recommend connecting C1 of loop filter close to charge pump pin.
22 GND — Ground Ground
23 GND — Ground Ground
24 VccMASH — — Digital supply. Connect to 3.3V with a 0.1µF and a 10µF capacitor to ground.
25 SCK I — SPI input clock. High impedance CMOS input. 1.6V – 3.3V logic.
26 SDI I — SPI input data. High impedance CMOS input. 1.6V – 3.3V logic.
27 VccBUF — — Output buffer supply. Connect to 3.3V with a 0.1µF capacitor to ground.
28 GND — Ground Ground
29 RFoutBM O — Differential output B Pair. 50Ω resistor pullup to VCC is integrated. Can be used as a synthesizer output or SYSREF output.
30 RFoutBP O — Differential output B Pair. 50Ω resistor pullup to VCC is integrated. Can be used as a synthesizer output or SYSREF output.
31 GND — Ground Ground
32 VccBUF — — Output buffer supply. Connect to 3.3V with a 0.1µF capacitor to ground.
33 NC — — Connect this pin to either VCC or ground through 1KΩ resistor. This does not affect the performance.
34 MUXout — — Multiplexed output pin. Can output: lock detect, SPI readback and diagnostics.
35 CSB — SPI chip select bar. High impedance CMOS input. 1.6V – 3.3V logic.
36 GND — Ground Ground
37 VccBUF — — Output buffer supply. Connect to 3.3V with a 0.1µF capacitor to ground.
38 GND — Ground Ground
39 RFoutAM O — Differential output A Pair. 50Ω resistor pullup to VCC is integrated.
40 RFoutAP O — Differential output A Pair. 50Ω resistor pullup to VCC is integrated.
41 GND — Ground Ground
42 VccBUF — — Output buffer supply. Connect to 3.3V with a 0.1µF capacitor to ground.
43 GND — Ground Ground
44 VccVCO2 — — VCO supply. Connect to 3.3V with a 0.1µF and a 10µF capacitor to ground.
45 VbiasVCO2 — — VCO bias. Requires connecting 1µF capacitor to ground.
46 SysRefReq I — SYSREF request input for JESD204B/C support.
47 VrefVCO2 — — VCO supply reference. Requires connecting 10µF capacitor to ground.
48 RECAL_EN I — Enables the automatic recalibration feature. Low on this pin does not trigger calibration. High on this means the calibration is triggered whenever the device is unlocked after certain delay. This pin has internally 200kΩ pull-up.
49 CDIV0 I 4-level pin Controls the Channel Divider along with CDIV2 and CDIV1 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
50 CDIV1 I 4-level pin Controls the Channel Divider along with CDIV0 and CDIV2 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
51 CDIV2 I 4-level pin Controls the Channel Divider along with CDIV1 and CDIV0 in Pin-mode option. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
52 GND — Ground Ground
53 VbiasVARAC — — VCO Varactor bias. Requires connecting 10µF capacitor to ground.
54 GND — Ground Ground
55 Vtune I — VCO tuning voltage input.
56 VrefVCO — — VCO supply reference. Requires connecting 10µF capacitor to ground.
57 VccVCO — — VCO supply. Connect to 3.3V with a 0.1µF and a 10µF capacitor to ground.
58 VregVCO — — VCO regulator node. Requires connecting 1µF capacitor to ground.
59 GND — Ground Ground
60 GND — Ground Ground
61 NC — NC Connect this pin to VCC through 1KΩ resistor.
62 NDIV5 I 4-level pin Integer N divider bit 5 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
63 NDIV4 I 4-level pin Integer N divider bit 4 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
64 NDIV3 I 4-level pin Integer N divider bit 3 in Pin-mode. This is part of NDIV5-NDIV0, 6 bit value for N divider setting. Refer Pin-mode description details in Pin-Mode Integer Frequency Generation for more details.
— DAP — Ground Die Attach Pad. Connect DAP to PCB ground plane using multiple vias for good thermal performance.
(1) I=Input; O=Output