SNAS849 December   2024 LMX2624-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

6.3.13 Pin-Mode Integer Frequency Generation

The LMX2624-SP has Pin-mode option to generate fixed frequency output with out any serial programming. The output frequency is generated based on the Pin setting in the Pin-mode option. The Integer N divider and Channel Divider can be set using the Pin-mode options.

A few rules of operation for these Pin-modes are as follows:

  • Set the pin-mode using CDIVx pins. All pin combinations of CDVIx pins except when connected to GROUND is consider as Pin-mode. The SPI control can not be used in Pin-mode. If CDIV2, CDIV1, and CDIV0 are tied to GROUND, the device is in SPI-mode.
  • The rise time for the supply needs to be <50 ms.
  • Fractional Numerator and Denominator not available in Pin-mode. Only N divider is set using the NDIV setting
  • CAL pin tied to VCC. When changing between Pin-mode frequency options, after the pins are changed, the CAL pin must be toggled.

NDIVx and CDIVx pins are four level pins. Four level pins are used to get more number of division values with less number of pins which helps to reduce the overall package size. NDIVx has total of six pins and CDIVx has three pins. 6 pins of NDIVx (NDIV5, NDIV4, NDIV3, NDIV2, NDIV1, NDIV0) with four levels can create total of 46 combinations, which means 4096 values. Similarly CDIVx (CDIV2, CDIV1, CDIV0) with four level pins have total of 43 = 64 combinations. Due to the four level pins, 9 pins are sufficient instead of 18 pins for two level pins. The four levels of pin are VL, VML, VMH and VH as shows in Figure 6-4. Use three 10-kΩ resistors across VCC and GROUND which have four levels including VCC, GROUND and two mid levels called VMH (Voltage Mid High) and VML (Voltage Mid Low).

LMX2624-SP Four Level Pins Implementation Figure 6-4 Four Level Pins Implementation

NDIVx provides total of 4096 integer divider options in Pin-mode. Numerator (NUM) and Denominator (DEN) is not available in Pin-mode for fractional PLL and is only possible through SPI-mode. The minimum value for N divider restriction for Pin-mode NDIVx values are similar to the SPI-mode option. Refer to Table 6-2 for the N divider minimum value setting.

All combinations of Channel Divider settings which are available in SPI-mode are also available in Pin-mode option using CDIVx pins. Refer to Table 6-11 for CDIVx settings in Pin-mode, CHDIV<4:0> settings in SPI-mode and the corresponding Channel Divider value. Based on the Channel Divider value needed, CDIV2, CDIV1, CDIV0 pins needed to be connected to one of the four levels.

Table 6-11 CDIVx Pin-Mode Divider Values
CDIV2 CDIV1 CDIV0 CHDIV<4:0> EQUIVALENT IN SPI MODE CHANNEL DIVIDER VALUE
VL VL VL 0 SPI mode
VL VML VL 1 2
VL VMH VL 2 4
VL VMH VH 3 6
VML VL VL 4 8
VML VL VH 5 12
VML VML VL 6 16
VML VML VH 7 24
VML VMH VL 8 32
VML VMH VH 9 48
VML VH VL 10 64
VML VH VH 11 96
VMH VL VL 12 128
VMH VL VH 13 192
VMH VML VL 14 256
VMH VML VH 15 384
VMH VMH VL 16 512
VMH VMH VH 17 768
VMH VH VL 18 1024
VMH VH VH 19 1536

OUTMUX2, OUTMUX1 and OUTMUX0 pins are used to select the RFOUTx based on Table 6-12.

Table 6-12 OUTMUX Settings
OUTMUX2 OUTMUX1 OUTMUX0 RFOUTA OUTPUT RFOUTB OUTPUT
0 0 0 Channel Divider Channel Divider
0 0 1 Channel Divider VCO
0 1 0 VCO Channel Divider
0 1 1 VCO VCO
1 0 0 Doubler Channel Divider
1 0 1 VCO Doubler
1 1 0 Doubler VCO
1 1 1 Doubler Doubler

Example Frequency Generation in Pin-mode:

Requirements:

RFOUTAx RF output frequency = 21000 MHz

Only one RF output required; No SYSREF.

Reference Input (OSCIN) frequency = 50 MHz

Mode required: Pin-mode; No software or SPI control available in the actual sub-system implementation.

For generating 21000 MHz, Doubler output needed at the output. The configuration is as below:

CDIVx pins need to be configured value other than GND. For example, connect CDIV2, CDIV1 and CDIV0 to VCC (All '1's).

OUTMUX2 = 1, OUTMUX1 = 1, OUTMUX0 = 0 (RFOUTA is configured for Doubler output).

MuteB is connected to GND for Muting the VCO path on RFOUTB.

REF_DBLR_EN is connected to VCC in this configuration for having the PFD to 100 MHz. The OSCIN 50 MHz is doubled using this input doubler to improve the phase noise performance.

VCO frequency = 10500 MHz for generating 21000 MHz after Doubler. NDIV value needs to be 10500 / 100 = 105. Connect NDIV5, NDIV4, NDIV3, NDIV2, NDIV1, NID0 pins to the resistor network equivalent to 105 value.

Convert decimal 105 into equivalent base 4 value for generating the configuration for NDIV pins.

(105)10 = (001221)4.

The NDIVx pins need to be connected to VL, VL, VML, VMH, VMH, VML respectively using the resistor network.

MuteA and MuteB pins are available in Pin-mode and can be used as required for Mute and Unmute.

Refer to Unused pins treatment table for configuring the connections for unused pins.

Driving 4-level Pins Using GPIOs:

Previous section described on creating VL, VML, VMH and VH levels using resistor network. This arrangement is sufficient if the RFOUTx frequency is fixed. For applications that require changes of frequency using pin-mode options, the NDIVx and CDIVx pins levels need to be changed as per the output frequency requirement. One option is to drive these 4-level pins using low speed precision DACs to create these four voltage levels which is complex.

Following arrangement can help in driving 4-level using GPIOs. See Table 6-13.

Table 6-13 Driving 4-level Pins Using GPIOs in Pin-mode
NxB NxA Nx Voltage level at Nx Pin
VL VL VL 0
VL VH VML VH/3
VH VL VMH 2* VH/3
VH VH VH VH

LMX2624-SP Driving 4 Level Pins Using GPIOs Figure 6-5 Driving 4 Level Pins Using GPIOs

The arrangement in Figure 6-5 needs to be created for which NDIVx and CDIVx pins need to be updated based on the output frequency requirement.