STDA033 October   2026 MSPM0G3105-Q1 , MSPM0G3106-Q1 , MSPM0G3107-Q1 , MSPM0G3505-Q1 , MSPM0G3506-Q1 , MSPM0G3507-Q1 , MSPM0L1227-Q1 , MSPM0L1228-Q1 , MSPM0L2227-Q1 , MSPM0L2228-Q1 , MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1.     How Does an Electromagnetic Field Start in a Circuit?
    2.     Near-Field and Far-Field Electromagnetic Fields
  5. 2Common Sources of EMI in Electronic Designs
    1. 2.1 Resistors
      1. 2.1.1 Equivalent Series Inductance (ESL)
      2. 2.1.2 Shunt Capacitance
      3. 2.1.3 Parasitic Capacitance to Ground
    2. 2.2 Capacitors
      1. 2.2.1 Equivalent Series Resistance (ESR)
      2. 2.2.2 Equivalent Series Inductance (ESL)
      3. 2.2.3 Leakage Resistance
      4. 2.2.4 Dielectric Absorption (Soakage)
    3. 2.3 Inductors
      1. 2.3.1 Direct Current Resistance (DCR)
      2. 2.3.2 Parasitic Capacitance
      3. 2.3.3 Core Losses (Magnetic Parasitics)
    4. 2.4 Summary of Discrete Component EMI Considerations
    5. 2.5 Design Deficiencies
    6. 2.6 Sources Specific to MCUs
      1. 2.6.1 Clock Circuits and Oscillators
    7. 2.7 Other Common Sources
      1. 2.7.1 High-Speed Digital Buses
      2. 2.7.2 I/O Output Transitions
      3. 2.7.3 Floating Components
      4. 2.7.4 External Environmental Sources
  6. 3Mitigation Techniques to Minimize EMI and Optimize Board Performance
    1. 3.1 Power Supply Capacitor Selection and Placement
    2. 3.2 Capacitor Placement
    3. 3.3 Layer Stack-Up Optimization
      1. 3.3.1 Good Stack-Up Traits
      2. 3.3.2 Stitching and Shielding Optimization Techniques
    4. 3.4 Trace Routing
    5. 3.5 Passive Pi Filtering
    6. 3.6 Shielding, Grounding, and Cable Boundaries
    7. 3.7 Transient and ESD Current Paths
  7. 4EMC Verification and Troubleshooting
    1. 4.1 Emissions and Immunity as Port Problems
    2. 4.2 Pre-Compliance Measurement Toolkit
    3. 4.3 A Frequency-to-Structure Debug Method
    4. 4.4 Interpreting Common Spectral Signatures
    5. 4.5 Integrated Design Review Checklist
  8. 5Conclusion

3.3.2 Stitching and Shielding Optimization Techniques

When a signal changes layers, its return current must also change physical location. An adjacent ground via gives return current a short vertical path between ground planes. Without it, the current may travel to a remote plane bond or decoupling capacitor, creating a large three-dimensional loop. That detour increases loop area and can create mode conversion, crosstalk, and radiation.

Practical placement guidance:

  • Place at least one ground stitching via adjacent to each high-speed signal via when the signal changes layers. For differential pairs, place ground vias symmetrically so the pair does not see an unbalanced transition.
  • If the signal changes from a layer referenced to one ground plane to a layer referenced to another ground plane, add ground vias connecting those planes near the signal via.
  • If the signal changes reference from ground to power, provide a high-frequency return bridge with a local decoupling capacitor between the two planes, placed close to the transition. Prefer avoiding this if possible.
  • For clock, reset, fast GPIO, SPI, SerDes, USB, Ethernet, LVDS, MIPI, and RF nets, treat every via transition as an RF structure, not as a simple topological connection.
  • Avoid via transitions over plane voids, near plane edges, or beside large anti-pad clearances that remove the local reference copper.
  • A compact signal-via plus ground-via cluster behaves more like a controlled vertical interconnect. At very high data rates, the complete geometry matters: signal barrel diameter, ground via distance, anti-pad shape, backdrill depth, pad stack, plane spacing, and symmetry all influence impedance and resonance.
  • Place a ground via near a high-speed signal via when both layers reference ground planes.
  • For differential pairs, keep signal and return-via geometry symmetric to limit common-mode conversion.
  • If the reference changes between power and ground, add a local high-frequency plane bridge with a capacitor, or preferably avoid the reference change.
  • At very high data rates, include anti-pad shape, via stub, barrel diameter, plane spacing, and backdrill in the interconnect model.
Table 3-3 Via Implementations and Cautions
Use caseInitial pitch / distanceWhyCautions
Signal via return stitching1mm to 3mm from the signal via when practicalKeeps the return current transition localRespect impedance, anti-pads, pair symmetry, and fabricator clearance
Differential pair layer transitionTwo ground vias or symmetric via pair near transitionReduces imbalance and common-mode conversionAvoid asymmetric anti-pad removal near only one side of the pair
Board-edge ground fenceλ / 20 at highest concern; often 2mm to 5mm for general digital boardsReduces fringing and edge radiationDo not assume it fixes a bad return path in the interior
Noisy converter boundary2mm to 5mm pitch around the hot region as a starting pointContains fields and ties local pours to the main referenceKeep switch node copper inside the boundary and away from fence gaps
Connector shield/chassis boundaryAs tight as mechanically reasonable near connector shell and ESD returnPrevents cable current from spreading into logic groundRequires a defined chassis/digital ground strategy
Large quiet copper pours10mm to 20mm grid for low-frequency equipotential supportPrevents floating copper and lowers plane impedanceDo not create isolated copper slivers or acid traps