Layer stack-up can play an important role in the EMI performance of a PCB. One important consideration is which layer high speed signals are routed on and where this layer is in relation to a ground layer. By routing high speed signals on planes immediately adjacent to a solid ground plane, the return path is shortened and localizes magnetic fields.

A good stack-up places every fast signal layer adjacent to a continuous reference plane. Thin dielectric spacing tightens field coupling, lowers loop inductance, and reduces the field that reaches the board edge. A six-layer board offers more opportunities for close signal-to-ground coupling than a four-layer board, but layer count alone does not guarantee EMC: plane continuity and actual routing are decisive.

In general, any signal and the signal return path form a loop. As this loop increases in size, the resulting radiated emissions become stronger as well. This is why minimization of these loops becomes important for EMI sensitive designs. 6-layer boards are often preferred when designing for EMI optimization as this allows a return reference ground plane to be located below both the top and bottom layers of the PCB, reducing the loop significantly, not only through proximity to the outer layer, but also due to the plane being closer to the outer layer due to the additional internal layers. This continuous ground plane provides a direct and low inductance return path, keeping the fields contained between the top layer and the second layer. Figure 3-4 shows a good 6-layer board stack up for EMI conscious designs. This makes sure that each signal plane always has an adjacent GND plane.

Figure 3-4 Example 6-Layer PCB Stack-Up

A practical four-layer arrangement commonly uses outer signal/component layers with internal ground and power. Since there is no option to have an adjacent GND plane to each signal layer (assuming both internal layers are not a solid GND plane), add ground pours to the top layer and bottom layer with adequate via stitching. Make sure that the via stitching is dense on these ground pours in order to mitigate a poorly connected plane which can result in even more unwanted EMI as it acts as an antenna in this case. The ground plane and power plane are the internal layers, so on the layer without an adjacent ground plane, using guard traces and maintaining tightly coupled signal/return pairs is recommended to reduce potential EMI problems. The outer layer farther from ground needs careful ground pour, stitching, and routing discipline. In either case, do not route a fast signal where its nearest plane is broken by an anti-pad field, slot, or keepout.

• Prefer high-speed microstrip over the closest solid ground plane or stripline between solid references.
• Use ground pours only when they are well connected; floating or weakly stitched copper can resonate.
• Treat connector regions as boundary structures with explicit return and shield-current paths.

Figure 3-5 Example 4-Layer PCB Stack-Up

A grounded guard trace can reduce electric-field coupling and provide a nearby return path, but only if it is connected to a low-impedance reference with sufficiently frequent vias. Otherwise it can become a resonant conductor. A via fence connects reference copper layers and reduces fringe-field leakage at board edges, noisy zones, RF structures, apertures, and connector boundaries.

A common starting guideline is to keep stitching-via pitch much smaller than the guided wavelength at the highest frequency of concern. Practical spacing must also reflect source geometry and the continuity required at the boundary.

The wavelength rule is a starting point, not a universal optimum. The fence must be close to the field source or boundary, tied to a quiet reference, and free of long gaps. Dense vias far from the actual current path add cost without repairing a return discontinuity in the board interior.

To integrate guard traces for 4-layer boards where there are high speed critical signals, first make sure the signal trace is as short as possible. Placing grounded copper traces on both sides of a high-speed or sensitive analog trace "captures" the radiated electric and magnetic fields, minimizing crosstalk with adjacent traces. They are also able to provide a low-impedance path for return currents, which is vital for preventing noisy signals from interfering with the rest of the board. For the best shielding, stitching vias must be spaced at intervals no greater than λ / 20 of the wavelength of the highest-frequency signal being protected to make sure this “fencing” acts as an effective EMI barrier.

Figure 3-6 Via Stitching and Guard Trace Implementation

A via fence is a row or ring of ground vias used to connect reference copper layers and reduce the leakage of fringe fields. Via fences are useful at board edges, around noisy switching zones, around RF or oscillator regions, alongside high-speed channels, and around connector boundaries. Via fences must be treated as a field-management tool, not as a universal cure for every EMI problem.

Where fences are most useful:

• Along board edges near high-speed traces, especially when traces approach an edge or connector.
• Around switch-mode power supplies, class-D outputs, motor drivers, high-current pulses, and crystal/clock regions.
• Around RF traces or antennas where the fence is part of a defined coplanar waveguide or shield boundary.
• At chassis-to-digital-ground transition zones, when the grounding concept intentionally separates shield current from quiet circuit ground.
• Around internal cutouts, slots, mounting holes, and mechanical keepouts that interrupt return current.
• A fence is less useful if it is far from the field source, if it is broken by long gaps, if it is tied to a noisy copper island, or if it forces the current return to cross an unintended path. Dense via fences can also create manufacturing costs, routing congestion, and plane perforation. Use them where they close a real RF path.