Another often overlooked optimization factor is the placement of the capacitors. The preferred placement shown in Figure 3-3 has three capacitors with the lowest value capacitor as close to the device pin as possible to reduce parasitic resistance and filter out higher frequency noise.

The ground connection for each capacitor is connected with a via to the ground plane layer with very short traces from the pad of the capacitor and the via. This is done to minimize the loop inductance and suppress noise that can be a result of larger loops which can function as an EM radiator. Target impedance turns a transient requirement into a design metric. If the load current changes by Delta-I and the allowed rail deviation is Delta-V, the power-distribution network must remain below Delta-V/Delta-I over the relevant bandwidth.

Target impedance is obtained by dividing the allowable rail-voltage deviation by the expected load-current step. The PDN must stay below that impedance across the bandwidth of the transient.

The highest-frequency capacitor must be closest to the supported pins with short, wide connections and adjacent power and ground vias. Bulk capacitance supports slower energy demand; local small-package capacitance supports fast edge current. Embedded package capacitance and tightly spaced power and ground planes extend the response to still higher frequency.

Figure 3-3 VIN Capacitor Placement Example Layout

Below is a summary of decoupling layout rules:

• Place the smallest-value, highest-frequency capacitor closest to the IC power and ground pins it supports.
• Give each high-speed IC local power and ground vias. Avoid routing through a long neck before reaching the planes.
• Place ground vias directly beside capacitor ground pads, and power vias directly beside capacitor power pads when the capacitor serves plane-to-pin current.
• Use multiple capacitor values only when their placement and parasitics are controlled. A poorly placed capacitor can be irrelevant above a few tens of MHz.
• Do not share a narrow ground return between a noisy load and a sensitive analog reference. Shared impedance turns current into voltage noise.

Bulk capacitors support lower-frequency load changes and prevent rail droop, but do not replace tight high-frequency bypassing. At the package and via scale, ESL often dominates. This is why a nearby 100nF capacitor can outperform a larger capacitor placed a few centimeters away for edge current.

Switching power stages deserve special treatment because they combine fast voltage edges, high current, magnetic fields, and nonlinear devices. Most regulator EMI problems originate from a few copper shapes: the switch node, the hot input loop, the gate-drive loop, and the diode/synchronous rectifier loop. Via stitching helps contain fields, but cannot compensate for a large switch loop or a switch node poured like a decorative logo.

Switching power stages combine high dv/dt, high di/dt, nonlinear devices, and magnetic components, so it is important to identify the commutation loops for each switch state. The highest priority loop is often the input ceramic capacitor through the switching devices and back. The switch node is a high-dv/dt electric-field source; the input and rectifier loops are high-di/dt magnetic-field sources.

• Place the input ceramic capacitor directly across the power-stage supply and return pins.
• Keep switch-node copper no larger than required for current and thermal performance.
• Route feedback and current sense away from the switch node and inductor; use quiet Kelvin sensing where appropriate.
• Keep motor current and recirculation paths out of logic and ADC returns.
• Use snubbers or gate-resistance tuning only after identifying the resonant elements and verifying device stress.
• Minimize the high-di/dt input loop from input capacitor to switch device and back. Put the input capacitor directly at the power stage pins.
• Keep switch-node copper as small as thermal and current requirements allow. Do not run quiet traces under or beside the switch node.
• Use a ground via wall around the converter region when it helps connect local ground pour to the reference plane and contain fields.
• Route feedback away from the switch node and inductor. Sense the output at the intended regulation point, not through a noisy power path.
• For motor drivers, separate power-current loops from control and sensing loops. Stitch the power-ground region well, but avoid injecting motor current into logic/ADC returns.