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TPS7A87 ACTIVE 500-mA, low-noise, high-PSRR, dual-channel adjustable ultra-low-dropout voltage regulator Alternative dual LDO with ultra-low-noise performance in a 4x4 WQFN package
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Product details

Parameters

Output options Adjustable Output, Fixed Output, Dual Output Iout (Max) (A) 0.5 Vin (Max) (V) 6 Vin (Min) (V) 2.7 Vout (Max) (V) 5.5 Vout (Min) (V) 1.2 Fixed output options (V) 1.2, 1.5, 1.8, 2.5, 3.3 Noise (uVrms) 65 Iq (Typ) (mA) 0.19 Thermal resistance θJA (°C/W) 74 Load capacitance (Min) (µF) 10 Rating Catalog Regulated outputs (#) 2 Features Enable, Output Discharge, Power Good, Sequencing and Monitoring Accuracy (%) 2 PSRR @ 100 KHz (dB) 20 Dropout voltage (Vdo) (Typ) (mV) 170 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

HTSSOP (PWP) 20 42 mm² 6.5 x 6.4 open-in-new Find other Linear regulators (LDO)

Features

  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power-Up Sequencing for DSP Applications
  • Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2
  • Fast Transient Response
  • Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V,
    and Dual Adjustable Outputs
  • Open Drain Power-On Reset with 120ms Delay
  • Open Drain Power Good for Regulator 1
  • Ultra Low 190µA (typ) Quiescent Current
  • 1µA Input Current During Standby
  • Low Noise: 65µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.

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Description

TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution.

The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.

These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1µA at TJ = +25°C.

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition), VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1.

The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the VOUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 10
Type Title Date
* Datasheet Dual-Output Low-Dropout Vltg Reg with Pwr Up Sequencing For Split Vo datasheet (Rev. I) Aug. 19, 2010
Application note LDO Noise Demystified (Rev. B) Aug. 18, 2020
Application note Using Thermal Calculation Tools for Analog Components (Rev. A) Aug. 30, 2019
Technical articles LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical articles LDO Basics: Preventing reverse current Jul. 25, 2018
Technical articles LDO basics: introduction to quiescent current Jun. 20, 2018
Application note LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Technical articles LDO basics: noise – part 1 Jun. 14, 2017
Application note Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) Jul. 05, 2000
User guide Low-Dropout, Dual-Output Line Regulator EVM Using the TPS70151 (Rev. A) Apr. 12, 2000

Design & development

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Reference designs

REFERENCE DESIGNS Download
Switched capacitor integrated buck (SCIB) power converter reference design
PMP22510 — This switched capacitor integrated buck (SCIB) converter is a highly-optimized design for use in a high-power, high-density single output power converter, operating from a wide-range 40-V to 60-V input rail to produce a 8.0-V, 5.0-V, 3.3-V or 1.8-V rail up to 40A of load current each phase. This (...)
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HTSSOP (PWP) 20 View options

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