LP2996A

AKTIV

DDR-Terminierungsregler mit Deaktivierungs-Pin, 1,5 A für DDR2/3/3L

Produktdetails

Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm² 4.9 x 6
  • 1.35V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • LP2998/8Q recommended for
    –40°C to 125°C
  • 1.35V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • LP2998/8Q recommended for
    –40°C to 125°C

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet LP2996A DDR Termination Regulator datasheet PDF | HTML 27 Jun 2014
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Limiting DDR Termination Regulators’ Inrush Current 23 Aug 2016

Design und Entwicklung

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Evaluierungsplatine

LP2998EVAL — Evaluierungsplatine für den LP2998

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

Benutzerhandbuch: PDF
Simulationsmodell

LP2996A PSpice Transient Model

SNOM562.ZIP (85 KB) - PSpice Model
Simulationsmodell

LP2996A Unencrypted PSpice Transient Model

SNOM564.ZIP (7 KB) - PSpice Model
Referenzdesigns

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This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDEP0067 — 66AK2Gx DSP + ARM-Prozessor-Leistungslösung – Referenzdesign

This reference design is  based on the 66AK2Gx multicore System-on-Chip (SoC) processor and companion TPS65911 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2Gx processor in a single device. This power solution design also includes (...)
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
HSOIC (DDA) 8 Ultra Librarian

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