THS6212

활성

고속, 차동 광대역 PLC/HPLC 라인 드라이버 증폭기

제품 상세 정보

Number of channels 1 Architecture PLC Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 10 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 28 BW at Acl (MHz) 285 Acl, min spec gain (V/V) 10 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 9 Iq per channel (typ) (mA) 23 Vos (offset voltage at 25°C) (max) (mV) 12 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Shutdown Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 65 Input bias current (max) (pA) 3500000 Offset drift (typ) (µV/°C) 155 GBW (typ) (MHz) 285 Iout (typ) (mA) 665 2nd harmonic (dBc) 86 3rd harmonic (dBc) 101 Frequency of harmonic distortion measurement (MHz) 1
Number of channels 1 Architecture PLC Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 10 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 28 BW at Acl (MHz) 285 Acl, min spec gain (V/V) 10 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 9 Iq per channel (typ) (mA) 23 Vos (offset voltage at 25°C) (max) (mV) 12 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Shutdown Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 65 Input bias current (max) (pA) 3500000 Offset drift (typ) (µV/°C) 155 GBW (typ) (MHz) 285 Iout (typ) (mA) 665 2nd harmonic (dBc) 86 3rd harmonic (dBc) 101 Frequency of harmonic distortion measurement (MHz) 1
VQFN (RHF) 24 20 mm² 5 x 4
  • Low power consumption:
    • Full-bias mode: 23 mA
    • Mid-bias mode: 17.5 mA
    • Low-bias mode: 11.9 mA
    • Low-power shutdown mode
    • IADJ pin for variable bias
  • Low noise:
    • Voltage noise: 2.5 nV/√Hz
    • Inverting current noise: 18 pA/√Hz
    • Noninverting current noise: 1.4 pA/√Hz
  • Low distortion:
    • –86-dBc HD2 (1-MHz, 100-Ω differential load)
    • –101-dBc HD3 (1-MHz, 100-Ω differential load)
  • High output current: > 665 mA (25-Ω load)
  • Wide output swing:
    • 49 VPP ( 28-V, 100-Ω differential load)
  • Wide bandwidth: 205 MHz (GDIFF = 10 V/V)
  • PSRR: >55 dB at 1 MHz for good isolation
  • Wide power-supply range: 10 V to 28 V
  • Thermal protection: 175°C (typical)
  • Alternative device with integrated common-mode buffer: THS6222
  • Low power consumption:
    • Full-bias mode: 23 mA
    • Mid-bias mode: 17.5 mA
    • Low-bias mode: 11.9 mA
    • Low-power shutdown mode
    • IADJ pin for variable bias
  • Low noise:
    • Voltage noise: 2.5 nV/√Hz
    • Inverting current noise: 18 pA/√Hz
    • Noninverting current noise: 1.4 pA/√Hz
  • Low distortion:
    • –86-dBc HD2 (1-MHz, 100-Ω differential load)
    • –101-dBc HD3 (1-MHz, 100-Ω differential load)
  • High output current: > 665 mA (25-Ω load)
  • Wide output swing:
    • 49 VPP ( 28-V, 100-Ω differential load)
  • Wide bandwidth: 205 MHz (GDIFF = 10 V/V)
  • PSRR: >55 dB at 1 MHz for good isolation
  • Wide power-supply range: 10 V to 28 V
  • Thermal protection: 175°C (typical)
  • Alternative device with integrated common-mode buffer: THS6222

The THS6212 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for use in broadband, wideband power line communications (PLC) line driver applications and is fast enough to support transmissions of 14.5-dBm line power up to 30 MHz.

The unique architecture of the THS6212 uses minimal quiescent current and still achieves very high linearity. Differential distortion under full bias conditions is –86-dBc at 1 MHz and reduces to only –71 dBc at 10 MHz. Fixed multiple bias settings allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an adjustable current pin (IADJ) is available to further lower the bias currents.

The wide output swing of 49 VPP (100-Ω differential load) with 28-V power supplies, coupled with over a 650-mA current drive (25-Ω load), allows for wide dynamic headroom that keeps distortion minimal.

The THS6212 is available in a 24-pin VQFN package.

The THS6212 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for use in broadband, wideband power line communications (PLC) line driver applications and is fast enough to support transmissions of 14.5-dBm line power up to 30 MHz.

The unique architecture of the THS6212 uses minimal quiescent current and still achieves very high linearity. Differential distortion under full bias conditions is –86-dBc at 1 MHz and reduces to only –71 dBc at 10 MHz. Fixed multiple bias settings allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an adjustable current pin (IADJ) is available to further lower the bias currents.

The wide output swing of 49 VPP (100-Ω differential load) with 28-V power supplies, coupled with over a 650-mA current drive (25-Ω load), allows for wide dynamic headroom that keeps distortion minimal.

The THS6212 is available in a 24-pin VQFN package.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
THS6222 활성 공통 모드 버퍼를 지원하는 차동 광대역 PLC 및 HPLC 라인 드라이버 Pin compatible QFN package with integrated common mode buffer and a wider operating supply range of 8V to 32V

기술 문서

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모두 보기3
유형 직함 날짜
* Data sheet THS6212 Differential Broadband PLC Line Driver Amplifier datasheet (Rev. E) PDF | HTML 2021/05/25
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017/03/28
Application note Noise Analysis for High Speed Op Amps (Rev. A) 2005/01/17

설계 및 개발

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평가 보드

THS6212EVM — THS6212 평가 모듈

The THS6212 Evaluation module (EVM) is used to evaluate the THS6212, which is single-port current-feedback architecture, differential line driver amplifier system in a 24-pin QFN package. The EVM is designed to quickly and easily demonstrate the functionality and performance of THS6212 in a gain (...)
사용 설명서: PDF
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시뮬레이션 모델

THS6212 PSpice Model

SBOMBP7.ZIP (62 KB) - PSpice Model
시뮬레이션 모델

THS6212 TINA-TI Reference Design

SBOM980.TSC (353 KB) - TINA-TI Reference Design
시뮬레이션 모델

THS6212 TINA-TI Spice Model

SBOM981.ZIP (11 KB) - TINA-TI Spice Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 다운로드
VQFN (RHF) 24 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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