SN65LVDS4
- Designed for Signaling Rates(1) up to:
- 500-Mbps Receiver
- Operates From a 1.8-V or 2.5-V Core Supply
- Available in 1.5-mm × 2-mm UQFN Package
- Bus-Terminal ESD Exceeds 2 kV (HBM)
- Low-Voltage Differential Signaling With Typical
Output Voltages of 350 mV Into a 100-Ω Load - Propagation Delay Times
- 2.1 ns Typical Receiver
- Power Dissipation at 250 MHz
- 40 mW Typical
- Requires External Failsafe
- Differential Input Voltage Threshold Less Than 50
mV - Can Provide Output Voltage Logic Level (3.3-V
LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
on External VDD Pin, Thus Eliminating External
LevelTranslation
The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.
技術文件
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檢視所有 10 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDS4 1.8-V High-Speed Differential Line Receiver datasheet (Rev. A) | PDF | HTML | 2015年 11月 30日 |
| Application brief | Level Shift No More: Support Low Voltage I/O Signals into a FPGA, Processor, or ASIC (Rev. A) | PDF | HTML | 2024年 8月 15日 | |
| Application brief | How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver | 2019年 1月 9日 | ||
| Application brief | How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter | 2018年 12月 28日 | ||
| Application brief | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| Application note | TMDS Clock Detection Solution in HDMI Sink Applications | 2017年 8月 23日 | ||
| Technical article | Get Connected: High-speed LVDS comparator | PDF | HTML | 2015年 6月 3日 | |
| EVM User's guide | SN65LVDS4 Evaluation Module | 2011年 7月 15日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
DDC2256AEVM — DDC2256A 256 通道電流輸入類比轉數位轉換器評估模組
DDC2256AEVM 評估模組 (EVM) 是用於 DDC2256A 的評估套件，這是一款是 256 通道、電流輸入、24 位元類比轉數位 (A/D) 轉換器。EVM 套件由 DUT 電路板和擷取板組成，包含兩個 DDC2256A 裝置、一個用於裝置通訊/配置的 FPGA、用於臨時資料儲存的 36MB 記憶體，以及一個用於連接 PC 的 USB 介面。EVM 包含所有必要的控制訊號及板載功率產生，因而大幅降低對外部設備的需求。最後，評估系統還為 Microsoft® Windows® 提供了易於使用的軟體。
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計
TIDA-01378 — 適用於上行 DOCSIS 3.1 應用的寬頻接收器參考設計
This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
參考設計
TIDA-01037 — 可實現最大 SNR 和取樣率的 20 位元 1 MSPS 隔離器最佳化資料採集參考設計
TIDA-01037 is a 20-bit, 1 MSPS isolated analog input data acquisition reference design that utilizes two different isolator devices to maximize signal chain SNR and sample rate performance. For signals requiring low jitter, such as ADC sampling clocks, TI’s ISO73xx family of low jitter (...)
參考設計
TIDA-00732 — 可實現最大 SNR 和採樣率的 18 位元 2 MSPS 隔離式資料採集參考設計
This “18-bit, 2-Msps Isolated Data Acquisition Reference Design to achieve maximum SNR and sampling rate” illustrates how to overcome performance-limiting challenges typical of isolated data acquisition system design:
- Maximizing sampling rate by minimizing propagation delay introduced by digital (...)
參考設計
TIDA-00823 — 具有 AC 與 DC 耦合固定增益放大器的 16 位元 1 GSPS 數位器參考設計
This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
參考設計
TIDA-00822 — 具有 AC 與 DC 耦合可變增益放大器的 16 位元 1 GSPS 數位器參考設計
This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| UQFN (RSE) | 10 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。