Packaging information
| Package | Pins SOIC (D) | 8 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 2,500 | LARGE T&R |
Features for the LM9061-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C4B
- Withstands 60-V Supply Transients
- Overvoltage Shut-OFF With VCC > 30 V
- Lossless Overcurrent Protection Latch-OFF
- Current Sense Resistor is Not Required
- Minimizes Power Loss With High Current Loads
- Programmable Delay of Protection Latch-OFF
- Gradual Turnoff to Minimize Inductive Load Transient Voltages
- CMOS Logic-Compatible ON and OFF Control Input
Description for the LM9061-Q1
The LM9061 family consists of charge-pump devices which provides the gate drive to an external power MOSFET of any size configured as a high-side driver or switch. This includes multiple parallel connected MOSFETs for very high current applications. A CMOS logic-compatible ON and OFF input controls the output gate drive voltage. In the ON state, the charge pump voltage, which is well above the available VCC supply, is directly applied to the gate of the MOSFET. A built-in 15-V Zener clamps the maximum gate to source voltage of the MOSFET. When commanded OFF a 110-µA current sink discharges the gate capacitances of the MOSFET for a gradual turnoff characteristic to minimize the duration of inductive load transient voltages and further protect the power MOSFET.
Lossless protection of the power MOSFET is a key feature of the LM9061. The voltage drop (VDS) across the power device is continually monitored and compared against an externally programmable threshold voltage. A small current-sensing resistor in series with the load, which causes a loss of available energy, is not required for the protection circuitry. If the VDS voltage, due to excessive load current, exceeds the threshold voltage, the output is latched OFF in a more gradual fashion (through a 10-µA output current sink) after a programmable delay time interval.