Ultra Low Noise Clock Jitter Cleaner With 6 Programmable Outputs - LMK04208

LMK04208 (ACTIVE)

Ultra Low Noise Clock Jitter Cleaner With 6 Programmable Outputs

 

Description

The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

Features

  • Ultra-Low RMS Jitter Performance
    • 111 fs, RMS Jitter (12 kHz to 20 MHz)
    • 123 fs, RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode when Input Clocks are Lost
      • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate of Up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO or External VCO Mode
  • Two Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • 6 LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control
  • 7 Differential Outputs, Up to 14 Single-Ended
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of Up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • 64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm)

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Parametrics Compare all products in Dual / Cascaded PLL

 
Number of Outputs
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
Number of Inputs
Input Level
RMS Jitter
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
Special Features
Operating Temperature Range (C)
Pin/Package
LMK04208 LMK04610 LMK04616 LMK04808 LMK04821 LMK04828 LMK04906
7    10    16    14    15    15    7   
LVCMOS
LVDS
LVPECL   
HCSL
HSDS
LVDS
LVPECL   
HCSL
HSDS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
HSDS
LCPECL
LVCMOS
LVDS
LVPECL   
HSDS
LCPECL
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
0.329    0.03    0.03    0.22    0.045    0.289    0.22   
3072    2000    2000    3072    2075    3080    2600   
2    2    4    2    3    3    3   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
LVCMOS
LVDS
LVPECL   
0.111    0.065    0.065    0.111    0.091    0.088    0.1   
2750    5800    5800    2750    365    2370    2370   
3072    6200    6200    3072    2075    3080    2600   
3.15    1.7    1.7    3.15    3.15    3.15    3.15   
3.45    3.465    3.465    3.45    3.45    3.45    3.45   
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire   
105C PCB temp
Holdover mode
JESD204B SYSREF Generation
Manual/auto switch
SPI   
105C PCB temp
Holdover mode
JESD204B SYSREF Generation
Manual and automatic switching between inputs
SPI   
uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator   
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire   
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire   
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire   
-40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85   
64WQFN    56QFN    144NFBGA    64WQFN    64WQFN    64WQFN    64WQFN   

WEBENCH® Designer LMK04208

Recommend Input Frequency Output Frequencies
 MHz
Input Frequency  MHz
 MHz  MHz