188.8.131.52 Clock Stretching
Clock stretching pauses a transaction by holding the SCL line LOW. The transaction cannot continue until the line is released HIGH again. Clock stretching occurs under the following conditions:
- The device is addressed (read or write) while programming the internal non-volatile memory. The SCA pin in actively pulled low until programming is completed or the programming cycles times out.
- The internal clock frequency is set to 1MHz and the I2C bus operates in fast-mode plus at 1MHz clock frequency. The device is be able to receive bytes of data at a fast rate, but may need more time to store a received byte or prepare another byte to be transmitted. The slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure.