SLVSE46A November 2017 – January 2018 TPS65680
The purpose of the EN_DLY timer is to delay entering ACTIVE state after power-up, in case the LS_CNTRL pin is permanently tied high. This allows to enable and preset all level shifter outputs before the level shifter starts toggling its outputs. The EN_DLY timer is re-started when the device is sitting in WAIT CNTRL HIGH state and the LS_CNTRL pit is pulled high. This allows the VGH rail to recover in case the active discharge function was turned ON during DISCHARGE STEP2 and / or WAIT CNTRL HIGH. The EN_DLY time constant is set in the register and should be only updated while the LS_CNTRL pin is low and the device is in STANDBY or WAIT CNTRL HIGHstate.