SLVSE46A November 2017 – January 2018 TPS65680
Figure 24 shows the format of a single read from a defined register address. First, the master issues a start condition followed by a seven-bit I2C address. Next, the master writes a zero to signify that it conducts a write operation. Upon receiving an acknowledge from the slave, the master sends the eight-bit register address across the bus. Following a second acknowledge TPS65680 sets the internal I2C register number to the defined value. Then the master issues a repeat start condition and the seven-bit I2C address followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the master releases the bus to the TPS65680. The TPS65680 then returns the eight-bit data value from the register on the bus. The master does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.