SLVSE46A November 2017 – January 2018 TPS65680
If the sequencer reads an invalid instruction, then the advancement of the address counter is stopped. Master channels, i.e. such level shifter outputs directly controlled by one of the C1-6 or D1-3 control bits keep their last state whereas slave channels (those controlled by C1A, C2A, C3A, C4A, C5A, C6A, D1A, D2A) may continue to toggle until the respective delays have been consumed. The sequence re-starts at the when the next LS_START pulse is detected.