SLVSE46A November 2017 – January 2018 TPS65680
The two-step power-down sequence is triggered by a falling edge on the LS_CNTRL pin as shown in Figure 6. The state of the level shifter outputs for each functional group (GCK, GSP, GCP, GGP, VSS) is programmable for each discharge phase ( and registers) as well as the duration of DISCHARGE STEP1, and the status of the VGH discharge function. DISCHARGE STEP1 duration is set by the D1_TIME constant defined in the register. D1_TIME must not be changed while the timer is running, i.e. the register must not be updated while in DISCHARGE STEP1. DISCHARGE STEP2 lasts for as long as VIN remains present, or until the LS_CNTRL pin toggles from low to high.
A typical discharge sequence begins with the LS_CNTRL pin being pulled low. All level shifter outputs are driven low with the exception of the CLEAR channels (GCKx) which are driven high. After 2 ms, the CLOCK (GCKx) and START (GSPx) channels are driven high together with VSS to complete the discharge sequence.