SLVSE46A November 2017 – January 2018 TPS65680
Each instruction takes one clock cycle to execute with the exception of JMP and EEQ which require two clock cycles. The SWP instructions takes at least 9 clock cycles. With the exceptions of the CXE and DXE commands, the level shifter outputs remain unchanged during the execution time, i.e. the current pattern state is extended by the number of clock cycles shown Table 2 in while a given instruction is being executed. There is a 2 clock cycle time delay between incrementing the address counter and a HV output toggling as shown in Figure 19.
|Instruction||Instruction Code||Execution time [SEQ_CLK cycles]|
|SWP||9||9 + <OVERLAP COUNT> + 2|