SLVSE46A November 2017 – January 2018 TPS65680
The SWP instruction compares the <CMP VALUE> to the content of register. If the value does not match then register is increment by 1 and the instruction is completed.
Otherwise register is reset to 0x00 and the content of the <REG ADDR> is temporarily stored. If <OVERLAP COUNT> is > 0, then register content is copied to <REG ADDR> and sequencer waits for <OVERLAP COUNT> + 3 clock cycles, else this step is skipped . Finally register content is copied to <REG ADDR> register and the temporarily stored value is stored in register.
A typical use case for the SWP instruction is to control the very low frequency ODD and EVEN output signals (GGP1 and GGP2) which toggle at the same time or with an overlap defined in <OVERLAP COUNT>. The <CMP VALUE> defines the toggle frequency. ODD and EVEN outputs can be controlled by register. The sequencer can address this register by its local address as shown in Table 1.The default setting of register (addressed by logic register address <REG ADDR>) defines the output level of the ODD and EVEN signals when the sequencer starts the pattern by entering the ACTIVE state. The default setting of register defines the inverted output level of both signals. When register got incremented to the value of <CMP VALUE> then actual <REG ADDR> is swapped with register content and ODD and EVEN signals are toggled.
Processing a SWP instruction requires 11 + <OVERLAP COUNT> clock cycles.