SLVSE46A November 2017 – January 2018 TPS65680
The EEQ instruction executes the following <LINE COUNT> number of commands if the content of the <REG ADDR> register matches <COMPARE VALUE>. Otherwise the next <LINE COUNT> number of instructions are skipped and execution resumes at the current address + <LINE COUNT> + 1. If the resulting target address exceeds the maximum allowed logical address of 53, the pattern sequence terminates immediately, similarly to executing an END instruction. <REG ADDR> denotes the logical address listed in Table 1 and is specified as a four-bit value. The use of non-specified addresses is legal but not recommended.
A typical use case for the EEQ instruction is a if-then-else construct consisting of a EEQ and a JMP instruction. In the example below, lines 4 and 5 are executed if register 0x15 equals 0xFF, else line 6 is executed. Lines 1, 2, and 7 are executed in either case.
Processing a EEQ instruction requires two clock cycles. Within the sequence, the level shifter output state preceding the EEQ instruction is extended by two clock cycles while processing the EEQ instruction as shown in the example below.
ADDR INST CLK OUTPUT STATE 1 CXE<1> 1 <1> 2 CXE<2> 2 <2> 3 EEQ(2,5,FF) 3 <2> <-- Execute next 2 lines if Reg 0x05 equals 0xFF 4 <2> For this example Reg 0x05 is assumed to contain 0xFF 4 CXE<3> 5 <3> 5 JMP(7) 6 <3> 7 <3> 6 CXE<4> <-- Line is skipped by JMP instruction 7 CXE<5> 8 <5>