SLVSE46A November 2017 – January 2018 TPS65680
The END instruction indicates the end of a sequence and stops the advancement of the address counter. Master channels, i.e. such level shifter outputs directly controlled by one of the C1-6 or D1-3 control bits keep their last state whereas slave channels (those controlled by C1A, C2A, C3A, C4A, C5A, C6A, D1A, D2A) may continue to toggle until the respective delays have been consumed. The sequence re-starts at the when the next LS_START pulse is detected.
If the LV bit is set to 1, <SET VALUE> is copied to register <REG ADDR> as the sequence is terminated. This is useful for changing the start address for the next frame. If the LV bit is set to 0, <SET VALUE> and <REG ADDR> are ignored. <REG ADDR> denotes the logical address listed in Table 1 and is specified as a four-bit value. The use of non-specified addresses is legal but not recommended.
Use of the END instruction is optional and not required for proper pattern execution. If the END instruction is omitted, the sequencer continues to the maximum pattern address and stops.