SLVSE46A November 2017 – January 2018 TPS65680
The I2C bus is a communications link between a master and a series of slave devices. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the master in all cases where the serial data line is bi-directional for data communication between the master and the slave terminals. Each device has an open-drain output to transmit data on the serial data line (SDA). An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. The TPS65680 has an I2C slave interface that supports standard-mode (100 kbit/s), fast-mode (400 kbit/s) and fast-mode plus (1 Mbit/s), and auto-increment addressing compatible with the I2C standard 3.0.
Data transmission is initiated with a start bit from the controller as shown in Figure 23. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the slave address bits are set for the device, then the device issues an acknowledge pulse and prepares the receive of register address and data. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given I2C transmission.