SLVSE46A November 2017 – January 2018 TPS65680
A pattern sequence consists of up to 54 24-bit wide instructions with logical addresses 0 to 53. A single logical 24-bit wide instruction is mapped to three physical and consecutive 8-bit wide registers. See in for details. Loading a single instruction requires writing to three registers, an entire sequence requires writing up to 162 registers (54 instructions x 3 registers). An instruction or sequence may be updated in whole or in part. Error or syntax checking is not performed. To load a sequence into volatile memory:
At this point the device is ready to execute a sequence. Apply the level shifter voltages, VGH, VGL1, VGL2 and pull the LS_CNTRL pin high to enter ACTIVE state and start the sequence.
For loading a pattern sequence into non-volatile memory, please refer to Programming section.