SBASAW9 December   2024 ADC168M102R-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog
        1. 6.3.1.1 Analog Inputs
        2. 6.3.1.2 Analog-to-Digital Converters (ADCs)
        3. 6.3.1.3 CONVST
        4. 6.3.1.4 CLOCK
        5. 6.3.1.5 RESET
        6. 6.3.1.6 REFIOx
      2. 6.3.2 Digital
        1. 6.3.2.1 Mode Selection Pins M0 and M1
        2. 6.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)
        3. 6.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1µs, Supported In Dual Output Modes)
        4. 6.3.2.4 2-Bit Counter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Modes and Reset
        1. 6.4.1.1 Power-Down Mode
        2. 6.4.1.2 Sleep Mode
        3. 6.4.1.3 Auto-Sleep Mode
        4. 6.4.1.4 Reset
    5. 6.5 Programming
      1. 6.5.1 Read Data Input (RD)
      2. 6.5.2 Serial Data Outputs (SDOx)
        1. 6.5.2.1 Mode I
        2. 6.5.2.2 Mode II (Half-Clock Mode Only)
        3. 6.5.2.3 Special Read Mode II (Half-Clock Mode Only)
        4. 6.5.2.4 Mode III
        5. 6.5.2.5 Fully Differential Mode IV (Half-Clock Mode Only)
        6. 6.5.2.6 Special Mode IV (Half-Clock Mode Only)
      3. 6.5.3 Programming the Reference DAC
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Grounding
        2. 8.4.1.2 Digital Interface
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
    4. 9.4 Trademarks
    5. 9.5 Receiving Notification of Documentation Updates
    6. 9.6 Support Resources
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7 Register Map

The ADC168M102R-SEP operation is controlled through a set of registers described in this section. Table 7-1 shows the register map. Set the contents of these 16-bit registers with the serial data input (SDI) pin. This pin is coupled to RD and clocked into the device on each CLOCK falling edge. All data are transferred MSB first. All register updates become active with the CLOCK rising edge after completing the 16-clock-cycle write access operation.

Table 7-1 Register Map
REGISTER BIT
15		 BIT
14		 BIT
13		 BIT
12		 BIT
11		 BIT
10		 BIT
9		 BIT
8		 BIT
7		 BIT
6		 BIT
5		 BIT
4		 BIT
3		 BIT
2		 BIT
1		 BIT
0
CONFIG C[1:0] R[1:0] PD[1:0] FE SR FC PDE CID CE A[3:0]
REFDAC1 Reserved RPD D[9:0]
REFDAC2 Reserved RPD D[9:0]
SEQFIFO S[1:0] SL[1:0] C11 C10 C21 C20 C31 C30 C41 C40 SP1 SP0 FD1 FD0
REFCM CMB[3:0] CMA[3:0] RB[3:0] RA[3:0]

To update the CONFIG register, a single write access is required. To update the contents of the other registers, a write access to the control register with the appropriate register address (bits A[3:0]) is required. A write access to the actual register follows thereafter. Figure 7-1 shows a diagram of updating these registers. Update the CONFIG register contents when issuing a register read out access with a single register write access. For example, change the device mode to full-clock mode when activating the REFDAC1 register read access. A full-clock mode is active on the 16th clock cycle of the CONFIG register update. The REFDAC1 data are then presented according to the full-clock mode timing.

To verify the register contents, issue a read access with CONFIG register bits A[3:0]. This access is described in the Programming the Reference DAC section, based on an example of verifying the reference DAC register settings. The register contents are always available on SDOA with the next read command. For example, if the FIFO is used, the register contents are presented after the FIFO read access completes (see Table 7-5 for more details). A complete read or write access requires a total of 40 clock cycles, during which a new access to the CONFIG register is not allowed.

ADC168M102R-SEP Updating Internal Register Settings (Example: Half-Clock Mode, CID = 1) Figure 7-1 Updating Internal Register Settings (Example: Half-Clock Mode, CID = 1)

Configuration (Config) Register

The configuration register selects the input channel, the activation of power-down modes, and the access to the sequencer and FIFO, reference selection, and reference DAC registers.

Figure 7-2 Config: Configuration Register (Default = 0000h)
15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
C[1:0] R[1:0] PD[1:0] FE SR FC PDE CID CE A[3:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-2 Config Register Field Descriptions
Bit Field Type Reset Description
15:14 C[1:0] R/W 0h Input channel selection.
These bits control the multiplexer input selection depending on the status of the PDE bit.
If PDE = 0 (default), the multiplexer is in fully differential mode and bits C[1:0] control the input multiplexer in the following manner:
0x = Conversion of analog signals at inputs CHx0P/CHx0N (default).
1x = Conversion of analog signals at inputs CHx1P/CHx1N.
If PDE = 1, the multiplexer is in pseudo-differential mode and bits C[1:0] control the input multiplexer in the following manner:
00 = Conversion of analog signal at input CHx0 versus the selected CMx or REFIOx (default).
01 = Conversion of analog signal at input CHx1 versus the selected CMx or REFIOx.
10 = Conversion of analog signal at input CHx2 versus the selected CMx or REFIOx.
11 = Conversion of analog signal at input CHx3 versus the selected CMx or REFIOx.
13:12 R[1:0] R/W 0h Configuration register update control.
These bits control the access to the CONFIG register.
00 = If M0 is 0, update of input selection bits C[1:0] only; if M0 is 1, no action (default).
01 = Update of the entire CONFIG register content enabled.
10 = Reserved for factory test; do not use. Changes potentially result in false behavior of the device.
11 = If M0 is 0, update of input selection bits C[1:0] only; if M0 is 1, no action.
11:10 PD[1:0] R/W 0h Power-down control.
These bits control the different power-down modes of the device.
00 = Normal operation (default).
01 = Device is in power-down mode (see the Power-Down Modes and Reset section for details).
10 = Device is in sleep power-down mode (see the Power-Down Modes and Reset section for details).
11 = Device is in Auto-sleep power-down mode (see the Power-Down Modes and Reset section for details).
9 FE R/W 0h FIFO enable control.
0 = The internal FIFO is disabled (default).
1 = The internal FIFO is enabled. The depth of the FIFO is controlled by SEQFIFO register bits FD[1:0].
8 SR R/W 0h Special read mode control.
0 = Special read mode is disabled (default).
1 = Special read mode is enabled; see Figure 6-7 and Figure 6-10 for details.
7 FC R/W 0h Full clock mode operation control.
0 = Full-clock mode operation is disabled (default); see Figure 5-1 for details.
1 = Full-clock mode operation is enabled; see Figure 5-2 for details.
6 PDE R/W 0h Pseudo-differential mode operation enable.
0 = 2x2 fully differential operation (default).
1 = 4x2 pseudo-differential operation.
5 CID R/W 0h Channel information disable.
0 = The channel information followed by conversion results or register contents are present on SDOx (default).
1 = Conversion data or register content is present on SDOx immediately after the falling edge of RD.
4 CE R/W 0h 2-bit counter enable (see Figure 7-3).
0: The internal counter is disabled (default).
1: The counter value is available prior to the conversion result on SDOx (active only if CID = 0).
3:0 A[3:0] R/W 0h Register access control.
These bits allow reading of the CONFIG register contents and control the access to the remaining registers of the device.
x000 = Update CONFIG register contents only (default)
0001 = Read CONFIG register content on SDOA with next access (see Figure 7-1).
x010 = Write to REFDAC1 register with next access (see Figure 7-1).
0011 = Read REFDAC1 register content on SDOA with next access (see Figure 7-1).
0100 = Generate software reset of the device.
x101 = Write to REFDAC2 register with next access (see Figure 7-1).
0110 = Read REFDAC2 register content on SDOA with next access (see Figure 7-1).
x111 = Update CONFIG register contents only.
1001 = Write to SEQFIFO register with next access (see Figure 7-1).
1011 = Read SEQFIFO register content on SDOA with next access (see Figure 7-1).
1100 = Write to REFCM register with next access (see Figure 7-1).
1110 = Read REFCM register content on SDOA with next access (see Figure 7-1).
ADC168M102R-SEP 2-Bit Counter Feature (Half-Clock Mode, Manual Channel Control, CID = 0) Figure 7-3 2-Bit Counter Feature (Half-Clock Mode, Manual Channel Control, CID = 0)

REFDAC1 and REFDAC2 Registers

Two reference DAC registers allow for enabling and setting up the appropriate value for each of the output string DACs that are connected to the REFIO1 and REFIO2 pins.

Figure 7-4 REFDAC1 Control Register (Default = 07FFh)
15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
Reserved RPD D[9:0]
R/W-0h R/W-1h R/W-3FFh
Table 7-3 REFDAC1 Register Field Descriptions
Bit Field Type Reset Description
15:11 Reserved R/W 0h Not used; always set to 0.
10 RPD R/W 1h DAC1 power down.
0 = Internal reference path 1 is enabled and the reference voltage is available at the REFIO1 pin.
1 = The internal reference path is disabled (default).
9:0 D[9:0] R/W 3FFh DAC1 setting bits.
These bits correspond to the settings of the internal reference DACs (compare REFIO section). The D9 bit is the MSB value of the DAC.
Default value is 3FFh (2.5V nom).
Figure 7-5 REFDAC2 Control Register (Default = 07FFh)
15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
Reserved RPD D[9:0]
R/W-0h R/W-1h R/W-3FFh
Table 7-4 REFDAC2 Register Field Descriptions
Bit Field Type Reset Description
15:11 Reserved R/W 0h Not used; always set to 0.
10 RPD R/W 1h DAC2 power down.
0 = Internal reference path 2 is enabled and the reference voltage is available at the REFIO2 pin.
1 = The internal reference path is disabled (default).
9:0 D[9:0] R/W 3FFh DAC2 setting bits.
These bits correspond to the settings of the internal reference DACs (compare REFIO section). The D9 bit is the MSB value of the DAC.
Default value is 3FFh (2.5V nom).

Sequencer/FIFO (SEQFIFO) Register

The ADC168M102R-SEP features a programmable sequencer that controls the switching of the ADC input multiplexer in pseudo-differential, automatic channel-selection mode only. When used, a single read pulse allows all stored conversion data to be read. A single CONVST is required to control the conversion of the entire sequence. If the sequencer is used, control CONVST and RD independently (see Figure 7-7 and Figure 7-8).

Additionally, a programmable FIFO is available on each channel that allows storing up to four conversion results. Both features are controlled using this register. If FIFO is used, contrl CONVST and RD independently. After activation of this feature, make sure the FIFO is full before being read for the first time.

If the FIFO is full and a new conversion starts, the contents are shifted by one and the oldest result is lost. Only when the sequencer is used are the entire FIFO contents lost (that is, all bits are automatically set to 0). The FIFO is used independently from the sequencer. When both are used, finish the complete sequence before reading the data out of the FIFO; otherwise, the data are potentially corrupted.

Table 7-5 contains details of the data readout requirements depending on the FIFO settings in automatic channel selection mode.

Table 7-5 Conversion Result Read Out In FIFO Mode
AUTOMATIC CHANNEL SELECTION
INPUT SIGNAL TYPE FE = 0 FE = 1
Fully differential input mode Read cycle length = 1 word.
One RD pulse required after each conversion.		 Read cycle length = 2 × FIFO length.
One RD pulse required for the entire FIFO content.
Pseudo-differential input mode Read cycle length = 1 word.
One RD pulse required after each conversion or after completing the sequence if S1 = 1 and S0 = 1.		 Read cycle length = 2 × sequencer length × FIFO length.
One RD pulse required for the entire FIFO content.
Figure 7-6 SEQFIFO: Sequencer and FIFO Register (Default = 0000h)(1)
15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
S[1:0] SL[1:0] C1[1:0] C2[1:0] C3[1:0] C4[1:0] SP[1:0] FD[1:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
(1) The sequencer is used in pseudo-differential mode only. Set this register before setting the REFCM register.
Table 7-6 SEQFIFO Register Field Descriptions
Bit Field Type Reset Description
15:14 S[1:0] R/W 0h Sequencer mode selection (see Figure 7-7) in pseudo-differential mode only.
These bits allow for the control of the number of CONVSTs required, and the behavior of the BUSY pin in sequencer mode.
0x = An individual CONVST is required with BUSY indicating each conversion (default).
10 = A single CONVST is required for the entire sequence with BUSY indicating each conversion (half-clock mode only).
11 = A single CONVST is required for the entire sequence with BUSY remaining high throughout the sequence (half-clock mode only).
13:12 SL[1:0] R/W 0h Sequencer length control.
These bits control the length of a sequence. Bits [11:6] are only active if SL > 00.
00 = Do not use; use mode I or II instead, where M0 is 0 (default).
01 = Sequencer length is 2; C1x (bits[11:10]) and C2x (bits[9:8]) define the actual channel selection.
10 = Sequencer length is 3; C1x (bits[11:10]), C2x (bits[9:8]) and C3x (bits[7:6]) define the actual channel selection.
11 = Sequencer length is 4; C1x (bits[11:10]), C2x (bits[9:8]), C3x (bits[7:6]), and C4x (bits[5:4]) define the actual channel selection.
11:10 C1[1:0] R/W 0h First channel in sequence selection bits.
9:8 C2[1:0] R/W 0h Second channel in sequence selection bits.
7:6 C3[1:0] R/W 0h Third channel in sequence selection bits.
5:4 C4[1:0] R/W 0h Fourth channel in sequence selection bits.
Bits [11:4] control the pseudo-differential input multiplexer channel selection in sequencer mode.
00 = CHA0 and CHB0 are selected for the next conversion (default).
01 = CHA1 and CHB1 are selected for the next conversion.
10 = CHA2 and CHB2 are selected for the next conversion.
11 = CHA3 and CHB3 are selected for the next conversion.
3:2 SP[1:0] R/W 0h Sequence position bits (read only).
These bits indicate the setting of the pseudo-differential input multiplexer in sequencer mode.
00 = Inputs selected using bits C1[1:0] are converted with next rising edge of CONVST (default).
01 = Inputs selected using bits C2[1:0] are converted with next rising edge of CONVST.
10 = Inputs selected using bits C3[1:0] are converted with next rising edge of CONVST.
11 = Inputs selected using bits C4[1:0] are converted with next rising edge of CONVST.
1:0 FD[1:0] R/W 0h FIFO depth control (see Figure 7-8).
These bits control the depth of the internal FIFO if CONFIG register bit FE is 1.
00 = One conversion result per channel is stored in the FIFO for burst read access (default).
01 = Two conversion results per channel are stored in the FIFO for burst read access.
10 = Three conversion results per channel are stored in the FIFO for burst read access.
11 = Four conversion results per channel are stored in the FIFO for burst read access.
ADC168M102R-SEP Sequencer Modes Figure 7-7 Sequencer Modes
ADC168M102R-SEP FIFO and Sequencer Operation Example Figure 7-8 FIFO and Sequencer Operation Example

Reference and Common-Mode Selection (REFCM) Register

For flexible adjustment of the common-mode voltage in pseudo-differential mode when simplifying the circuit layout, the ADC168M102R-SEP provides this register. This register assigns one of the CMx inputs as a reference for each input signal. According to the register settings, the CMx signals are internally connected to the appropriate negative input of each ADC.

Additionally, this register also allows flexible assignment of one internal reference DAC output as a reference for each channel in both fully- and pseudo-differential modes.

Figure 7-9 REFCM: Reference and Common-Mode Selection Register (Default = 0000h)(1)
15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
CMB[3:0] CMA[3:0] RB[3:0] RA[3:0]
R/W-0h R/W-0h R/W-0h R/W-0h
(1) Set this register after setting the SEQFIFO register.
Table 7-7 REFCM Register Field Descriptions
Bit Field Type Reset Description
15:8 CMxx R/W 0h Common-mode source selection bits (per input channel).
These bits allow selection of the CMx input pins or the internal reference source as common-mode for pseudo-differential inputs B[3:0] and A[3:0]. The selected signal is connected to the negative input of the corresponding ADC.
0 = External common-mode source through CMx (default).
1 = Internal common-mode source = REFIOx, depending on settings of bits Rx[3:0].
7 RB3 R/W 0h Internal reference DAC output selection for CHB3 in pseudo-differential mode, or channel CHB1P, CHB1N in fully differential mode.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
6 RB2 R/W 0h Internal reference DAC output selection for CHB2 in pseudo-differential mode only.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
5 RB1 R/W 0h Internal reference DAC output selection for CHB1 in pseudo-differential mode only.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
4 RB0 R/W 0h Internal reference DAC output selection for CHB0 in pseudo-differential mode, or channel CHB0P, CHB0N in fully differential mode.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
3 RA3 R/W 0h Internal reference DAC output selection for CHA3 in pseudo-differential mode, or channel CHA1P, CHA1N in fully differential mode.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
2 RA2 R/W 0h Internal reference DAC output selection for CHA2 in pseudo-differential mode only.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
1 RA1 R/W 0h Internal reference DAC output selection for CHA1 in pseudo-differential mode only.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.
0 RA0 R/W 0h Internal reference DAC output selection for CHA0 in pseudo-differential mode, or channel CHA0P, CHA0N in fully differential mode.
0 = Internal reference source REFIO1 selected (default).
1 = Internal reference source REFIO2 selected.