|
| AOCDL
(Bit 7): Overload in Discharge latch |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| AOCD
(Bit 6): Overload in Discharge |
|
1
= |
Enabled
(default) |
|
0
= |
Disabled |
| | |
| OCD2 (Bit 5): Overcurrent in Discharge 2nd Tier |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| OCD1 (Bit 4): Overcurrent in Discharge 1st Tier |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| OCC2 (Bit 3): Overcurrent in Charge 2nd Tier |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| OCC1 (Bit 2): Overcurrent in Charge 1st Tier |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| COV (Bit 1): Cell Overvoltage |
| 1 = | Enabled (default) |
| 0 = | Disabled |
| | |
| CUV (Bit 0): Cell Undervoltage |
| 1 = | Enabled (default) |
| 0 = | Disabled |