SLUUCP8A June 2024 – April 2025 BQ41Z50
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | Configuration | GPIO Sealed Access Config | H2 | 0x0000 | 0x000F | 0x0000 | Hex |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | RSVD |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | RSVD | RSVD | RSVD | LEDCNTLC_PIN22 | LEDCNTLB_PIN21 | LEDCNTLA_PIN20 | DISP_PIN17 |
| RSVD (Bits 15–4): Reserved. Do not use. | ||
| LEDCNTLC_PIN22 (Bit 3): LEDCNTLC (Pin 22) SEALED mode access | ||
| 1 = | Enabled | |
| 0 = | Disabled | |
| LEDCNTLB_PIN21 (Bit 2): LEDCNTLB (Pin 21) SEALED mode access | ||
| 1 = | Enabled | |
| 0 = | Disabled | |
| LEDCNTLA_PIN20 (Bit 1): LEDCNTLA (Pin 20) SEALED mode access | ||
| 1 = | Enabled | |
| 0 = | Disabled | |
| DISP_PIN17 (Bit 0): DISP (Pin 17) SEALED mode access | ||
| 1 = | Enabled | |
| 0 = | Disabled | |