SLUUCP8A June 2024 – April 2025 BQ41Z50
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | AFE | OCC Wake Delay 1 | H1 | 0x0 | 0xFF | 0xFF | Hex |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SC_CC_WAKE_DLY1 |
| SC_CC_WAKE_DLY1 (Bits 7-0): Lower 8 bits of the CC_WAKE delay bits 7:0. DLY2 has to be written first and then DLY1. OCC Wake Delay is (CC_WAKE_DLY2 * 256 + CC_WAKE_DLY1 + 13) * 0.55ms. 0x000 is disabled, 0x001 is 1.1ms, 0x002 is 1.65ms, 0x003 is 2.2ms, .., 0x1ff is 288.2ms. |