SNVSC75B April 2023 – September 2025 LM5171-Q1
PRODUCTION DATA
Table 7-1 lists the memory-mapped registers for the REGFIELD registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 3h | CLEAR_FAULTS | CLEAR_FAULTS | Section 7.9.1 |
| 78h | FAULT_STATUS | FAULT_STATUS | Section 7.9.2 |
| D0h | DEVICE_STATUS_1 | DEVICE_STATUS_1 | Section 7.9.3 |
| D1h | DEVICE_STATUS_2 | DEVICE_STATUS_2 | Section 7.9.4 |
Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CLEAR_FAULTS is shown in Table 7-3.
Return to the Summary Table.
Clear all latched status flags in 0x78 register
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLEAR_FAULTS | R/W | 0h | Accessing the address is enough to clear fault |
FAULT_STATUS is shown in Table 7-4.
Return to the Summary Table.
Fault status
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | IPK_FAULT | R | 0h | IPK float detection
0h = no fault 1h = fault |
| 6 | VREF_FAULT | R | 0h | VREF to VDD short detection
0h = no fault 1h = fault |
| 5 | BOOTUV1 | R | 0h | Boot UV (HB-SW undervoltage) Channel 1
0h = no fault 1h = fault |
| 4 | BOOTUV2 | R | 0h | Boot UV (HB-SW undervoltage) Channel 2
0h = no fault 1h = fault |
| 3 | ILIM1 | R | 0h | Current limit Channel 1
0h = no fault 1h = fault |
| 2 | ILIM2 | R | 0h | Current limit Channel 2
0h = no fault 1h = fault |
| 1 | OVP | R | 0h | Overvoltage fault 0h = no fault 1h = fault |
| 0 | TSD | R | 0h | Thermal shutdown fault
0h = no fault 1h = fault |
DEVICE_STATUS_1 is shown in Table 7-5.
Return to the Summary Table.
Informational bits about the part status
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | EN1 | R | 0h | Channel 1 enable status
0h = Channel 1 disabled 1h = Channel 1 enabled |
| 6 | EN2 | R | 0h | Channel 2 enable status
0h = Channel 2 disabled 1h = Channel 2 enabled |
| 5 | DEM1 | R | 0h | Channel 1 DEM status
0h = Channel 1 FPWM 1h = Channel 1 DEM |
| 4 | DEM2 | R | 0h | Channel 2 DEM status
0h = Channel 2 FPWM 1h = Channel 2 DEM |
| 3 | DIR1 | R | 0h | DIR 1 status
0h = DIR1 low 1h = DIR1 high |
| 2 | DIR2 | R | 0h | DIR 2 status
0h = DIR2 low 1h = DIR2 high |
| 1 | DIR_INVALID1 | R | 0h | Invalid DIR1 command
0h = Valid DIR1 command 1h = Invalid DIR1 command |
| 0 | DIR_INVALID2 | R | 0h | Invalid DIR2 command
0h = Valid DIR2 command 1h = Invalid DIR2 command |
DEVICE_STATUS_2 is shown in Table 7-6.
Return to the Summary Table.
Informational bits about the part status
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | OSC_FAULT | R | 0h | OSC short detection
0h = No OSC fault 1h = OSC fault |
| 6 | UVLO | R | 0h | UVLO status
0h = Not in UVLO 1h = In UVLO (UVLO<2.5V) |
| 5 | OPT | R | 0h | OPT pin status
0h = OPT low 1h = OPT high |
| 4 | SS1_DONE | R | 0h | SS channel 1 completion status
0h = SS1 not done 1h = SS1 done |
| 3 | SS2_DONE | R | 0h | SS channel 2 completion status
0h = SS2 not done 1h = SS2 done |
| 2 | SD | R | 0h | SD/DT pin status
0h = Part not in SD 1h = Part in SD |
| 1 | ADAPT_DT | R | 0h | Adaptive deadtime status
0h = No adaptive deadtime 1h = Adaptive deadtime |
| 0 | VCC_UV | R | 0h | VCC UV status
0h = VCC not in UV 1h = VCC in UV |